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Cortex-M3 Processor Registers
2.7.4.11 NVIC_ISPR0 Register (Offset = 200h) [reset = X]
NVIC_ISPR0 is shown in
and described in
.
Irq 0 to 31 Set Pending This register is used to force interrupts into the pending state and determine which
interrupts are currently pending.
interrupts are currently pending.
Figure 2-81. NVIC_ISPR0 Register
31
30
29
28
27
26
25
24
SETPEND31
SETPEND30
SETPEND29
SETPEND28
SETPEND27
SETPEND26
SETPEND25
SETPEND24
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
23
22
21
20
19
18
17
16
SETPEND23
SETPEND22
SETPEND21
SETPEND20
SETPEND19
SETPEND18
SETPEND17
SETPEND16
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
15
14
13
12
11
10
9
8
SETPEND15
SETPEND14
SETPEND13
SETPEND12
SETPEND11
SETPEND10
SETPEND9
SETPEND8
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
7
6
5
4
3
2
1
0
SETPEND7
SETPEND6
SETPEND5
SETPEND4
SETPEND3
SETPEND2
SETPEND1
SETPEND0
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-107. NVIC_ISPR0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
SETPEND31
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current state.
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current state.
30
SETPEND30
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current state.
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current state.
29
SETPEND29
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current state.
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current state.
28
SETPEND28
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current state.
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current state.
27
SETPEND27
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current state.
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current state.
26
SETPEND26
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current state.
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current state.
25
SETPEND25
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current state.
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current state.
24
SETPEND24
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current state.
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current state.
23
SETPEND23
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current state.
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current state.
22
SETPEND22
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current state.
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current state.
21
SETPEND21
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit pends the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current state.
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current state.
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SWCU117A – February 2015 – Revised March 2015
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