Texas Instruments CC2650DK ユーザーズマニュアル
Cortex-M3 Processor Registers
2.7.4.42 ID_PFR0 Register (Offset = D40h) [reset = X]
ID_PFR0 is shown in
and described in
Processor Feature 0
Figure 2-112. ID_PFR0 Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
STATE1
STATE0
R-X
R-3h
R-X
Table 2-138. ID_PFR0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
7-4
STATE1
R
3h
State1 (T-bit == 1) 0x0: N/A 0x1: N/A 0x2: Thumb-2 encoding with
the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-
bit basic instructions (Note non-basic 32-bit instructions can be
added using the appropriate instruction attribute, but other 32-bit
basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2
basic instructions
the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-
bit basic instructions (Note non-basic 32-bit instructions can be
added using the appropriate instruction attribute, but other 32-bit
basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2
basic instructions
3-0
STATE0
R
X
State0 (T-bit == 0) 0x0: No ARM encoding 0x1: N/A
185
SWCU117A – February 2015 – Revised March 2015
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