Texas Instruments CC2650DK ユーザーズマニュアル
Introduction
6.1.4.2.1 Clock Gating
As seen in
, the peripheral modules have conditional clock gates that depend on the system
CPU mode. The clock of a module may be enabled or disabled when the system CPU mode changes.
Example:
•
[PRCM:I2CCLKGR.CLK_EN] = 1
•
[PRCM:I2CCLKGS.CLK_EN] = 0
•
[PRCM:I2CCLKGDS.CLK_EN] = 1
These settings will result in the I
2
C clock running when the system CPU is in run mode and deepsleep
mode, while the I²C clock will be disabled when system CPU is in sleep mode.
NOTE:
When set in deepsleep mode, the system CPU will remain in sleep mode for a few clock
cycles during the transition. An application that requires a continuous module clock will
enable all clock-gate registers for the module during the transition while the system CPU
changes modes.
enable all clock-gate registers for the module during the transition while the system CPU
changes modes.
Because power cycling of a power domain overrides clock gate registers, disabling the module clocks
before powering down a power domain is not required.
before powering down a power domain is not required.
6.1.4.2.2 Scalar to GPT
A scalar to GPTs is available to enable GPTs to count at a slower frequency than SYSBUS clock. The
setting in the [PRCM:GPTCLKDIV] register is valid for all GPTs in the system.
setting in the [PRCM:GPTCLKDIV] register is valid for all GPTs in the system.
6.1.4.2.3 Scalar to WDT
There is a scalar with a fixed-division ratio of 32 of the MCU clock that is present. The watchdog counts at
a constant speed regardless of the [PRCM:INFCLKDIVR], the [PRCM:INFCLKDIVS], and the
[PRCM:INFCLKDIVDS] register settings as long as the MCU clock is not changing between the SCLK_HF
and SCLK_LF as a clock source.
a constant speed regardless of the [PRCM:INFCLKDIVR], the [PRCM:INFCLKDIVS], and the
[PRCM:INFCLKDIVDS] register settings as long as the MCU clock is not changing between the SCLK_HF
and SCLK_LF as a clock source.
6.1.4.3
Clocks in AON_VD
All modules in AON_VD run on SCLK_LF except AUX_PD. Clocks to AUX_PD are user configurable.
6.1.5 Power Modes
The flexibility of the CC26xx power management allows many different configurations to achieve a low-
power application. This section describes the power modes, as defined by TI-RTOS, which covers a range
of power-saving modes from low-power savings with fast-cycling time to high-power savings with long-
cycling time.
power application. This section describes the power modes, as defined by TI-RTOS, which covers a range
of power-saving modes from low-power savings with fast-cycling time to high-power savings with long-
cycling time.
provides an overview of the power modes defined in TI-RTOS.
422 Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated