Texas Instruments CC2650DK ユーザーズマニュアル
PRCM Registers
6.2.1.37 WARMRESET Register (Offset = 110h) [reset = X]
WARMRESET is shown in
and described in
.
WARM Reset Control And Status
Figure 6-43. WARMRESET Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
WR_TO_PINR
LOCKUP_STA
WDT_STAT
ESET
T
R-X
R/W-X
R-X
R-X
Table 6-45. WARMRESET Register Field Descriptions
Bit
Field
Type
Reset
Description
31-3
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
WR_TO_PINRESET
R/W
X
0: No action 1: A warm system reset event triggered by the below
listed sources will result in an emulated pin reset. Warm reset
sources included: ICEPick sysreset System CPU reset request,
CPU_SCS:AIRCR.SYSRESETREQ System CPU Lockup WDT
timeout An active ICEPick block system reset will gate all sources
except ICEPick sysreset SW can read
AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the
last reset resulting in a full power up sequence. WARMRESET in
this register is set in the scenario that WR_TO_PINRESET=1 and
one of the above listed sources is triggered.
listed sources will result in an emulated pin reset. Warm reset
sources included: ICEPick sysreset System CPU reset request,
CPU_SCS:AIRCR.SYSRESETREQ System CPU Lockup WDT
timeout An active ICEPick block system reset will gate all sources
except ICEPick sysreset SW can read
AON_SYSCTL:RESETCTL.RESET_SRC to find the source of the
last reset resulting in a full power up sequence. WARMRESET in
this register is set in the scenario that WR_TO_PINRESET=1 and
one of the above listed sources is triggered.
1
LOCKUP_STAT
R
X
0: No registred event 1: A system CPU LOCKUP event has occured
since last SW clear of the register. A read of this register clears both
WDT_STAT and LOCKUP_STAT.
since last SW clear of the register. A read of this register clears both
WDT_STAT and LOCKUP_STAT.
0
WDT_STAT
R
X
0: No registered event 1: A WDT event has occured since last SW
clear of the register. A read of this register clears both WDT_STAT
and LOCKUP_STAT.
clear of the register. A read of this register clears both WDT_STAT
and LOCKUP_STAT.
466
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated