Texas Instruments CC2650DK ユーザーズマニュアル
PRCM Registers
6.2.3.5
AUXCTL Register (Offset = 10h) [reset = X]
AUXCTL is shown in
and described in
AUX Control This register contains events and control signals for the AUX domain.
Figure 6-71. AUXCTL Register
31
30
29
28
27
26
25
24
RESET_REQ
RESERVED
R/W-X
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
SCE_RUN_EN
SWEV
AUX_FORCE_
ON
R-X
R/W-X
R/W-X
R/W-X
Table 6-75. AUXCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31
RESET_REQ
R/W
X
Reset request for AUX. Writing 1 to this register will assert reset to
AUX. The reset will be held until the bit is cleared again. 0: AUX
reset pin will be deasserted 1: AUX reset pin will be asserted
AUX. The reset will be held until the bit is cleared again. 0: AUX
reset pin will be deasserted 1: AUX reset pin will be asserted
30-3
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
SCE_RUN_EN
R/W
X
Enables (1) or disables (0) AUX_SCE execution. AUX_SCE
execution will begin when AUX Domain is powered and either this or
AUX_SCE:CTL.CLK_EN is set. Setting this bit will assure that
AUX_SCE execution starts as soon as AUX power domain is woken
up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX power domain
has been off) 0: AUX_SCE execution will be disabled if
AUX_SCE:CTL.CLK_EN is 0 1: AUX_SCE execution is enabled.
execution will begin when AUX Domain is powered and either this or
AUX_SCE:CTL.CLK_EN is set. Setting this bit will assure that
AUX_SCE execution starts as soon as AUX power domain is woken
up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX power domain
has been off) 0: AUX_SCE execution will be disabled if
AUX_SCE:CTL.CLK_EN is 0 1: AUX_SCE execution is enabled.
1
SWEV
R/W
X
Writing 1 sets the software event to the AUX domain, which can be
read through AUX_WUC:WUEVFLAGS.AON_SW. This event is
normally cleared by AUX_SCE through the
AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0
to this register. Reading 0 means that there is no outstanding
software event for AUX. Note that it can take up to 1,5 SCLK_LF
clock cycles to clear the event from AUX.
read through AUX_WUC:WUEVFLAGS.AON_SW. This event is
normally cleared by AUX_SCE through the
AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0
to this register. Reading 0 means that there is no outstanding
software event for AUX. Note that it can take up to 1,5 SCLK_LF
clock cycles to clear the event from AUX.
0
AUX_FORCE_ON
R/W
X
Forces the AUX domain into active mode, overriding the requests
from AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and
AUX_WUC:MCUBUSCTL. Note that an ongoing
AUX_WUC:PWROFFREQ will complete before this bit will set the
AUX domain into active mode. MCU must set this bit in order to
access the AUX peripherals. The AUX domain status can be read
from PWRSTAT.AUX_PD_ON 0: AUX is allowed to Power Off,
Power Down or Disconnect. 1: AUX Power OFF, Power Down or
Disconnect requests will be overruled
from AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and
AUX_WUC:MCUBUSCTL. Note that an ongoing
AUX_WUC:PWROFFREQ will complete before this bit will set the
AUX domain into active mode. MCU must set this bit in order to
access the AUX peripherals. The AUX domain status can be read
from PWRSTAT.AUX_PD_ON 0: AUX is allowed to Power Off,
Power Down or Disconnect. 1: AUX Power OFF, Power Down or
Disconnect requests will be overruled
498
Power, Reset, and Clock Management
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated