Texas Instruments CC2650DK ユーザーズマニュアル
CACHE
rom
FLASH
icode/dcode
sysbus
icode/dcode
sysbus
USERCODE and
SYSCODE
address space
BROM
address space
USERCODE and
SYSCODE
address space
CACHE
rom
FLASH
SYSCODE
address space
icode/dcode
USERCODE
address space
sysbus
USERCODE and
SYSCODE
address space
BROM
address space
VIMS Configurations
Figure 7-5. VIMS Module in Cache Mode
In cache mode, all CPU accesses to the flash SYSCODE address space are directed to the cache first.
The cache looks up the input address in the internal tag RAM to determine whether the access is a cache
hit or a cache miss.
The cache looks up the input address in the internal tag RAM to determine whether the access is a cache
hit or a cache miss.
In the case of a cache miss, the access is forwarded to the Flash block. The response from the Flash
block is routed back to the cache, then the cache is updated.
block is routed back to the cache, then the cache is updated.
In the case of a cache hit, the data is fetched directly from the cache RAM.
The cache also contains a line buffer because the cache RAM word size is 64 bits. The objective of the
line buffer is to prevent refetching the 32-bit part of the data that has already been fetched (but not used)
in the previous access. The line buffer prevents both TAG and CACHE lookup if the data is already in the
line buffer.
line buffer is to prevent refetching the 32-bit part of the data that has already been fetched (but not used)
in the previous access. The line buffer prevents both TAG and CACHE lookup if the data is already in the
line buffer.
The cache line buffer is cleared as a part of the invalidation scheme.
7.1.1.4
Split Mode
In this mode the RAM block will function as two 4K 4-way random replacement caches for Flash block.
One cache for CPU accesses to the Flash SYSCODE address space, and one cache for CPU accesses
to the Flash USERCODE address space. The GPRAM space will not be available in this mode. Also, all
system bus accesses to the Flash block are routed directly to the Flash block.
One cache for CPU accesses to the Flash SYSCODE address space, and one cache for CPU accesses
to the Flash USERCODE address space. The GPRAM space will not be available in this mode. Also, all
system bus accesses to the Flash block are routed directly to the Flash block.
Figure 7-6. VIMS Module in Split Mode
533
SWCU117A – February 2015 – Revised March 2015
Versatile Instruction Memory System (VIMS)
Copyright © 2015, Texas Instruments Incorporated