Texas Instruments CC2650DK ユーザーズマニュアル
Factory Configuration (FCFG)
9.2.1.29 FLASH_P_R_PV Register (Offset = 178h) [reset = X]
FLASH_P_R_PV is shown in
and described in
Flash Program, Read, and Program Verify
Figure 9-50. FLASH_P_R_PV Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PH
RH
PVH
PVH2
R-2h
R-6Eh
R-2h
R-X
Table 9-52. FLASH_P_R_PV Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
PH
R
2h
Program hold time in half-microseconds after SAFELV goes low.
Value will be converted to number of FCLK cycles by the flash
device driver and the converted value is written to
FLASH:FSM_P_OH.PGM_OH when an erase/program operation is
initiated.
Value will be converted to number of FCLK cycles by the flash
device driver and the converted value is written to
FLASH:FSM_P_OH.PGM_OH when an erase/program operation is
initiated.
23-16
RH
R
6Eh
Read hold/mode transition time in cycles. Value will be written to the
RD_H field bits[7:0] of the FSM_RD_H register in the flash module
by the flash device driver when an erase/program operation is
initiated.
RD_H field bits[7:0] of the FSM_RD_H register in the flash module
by the flash device driver when an erase/program operation is
initiated.
15-8
PVH
R
2h
Program verify hold time in half-microseconds after SAFELV goes
low. Value will be converted to number of FCLK cycles by the flash
device driver and the converted value is written to
FLASH:FSM_PE_VH.PGM_VH when an erase/program operation is
initiated.
low. Value will be converted to number of FCLK cycles by the flash
device driver and the converted value is written to
FLASH:FSM_PE_VH.PGM_VH when an erase/program operation is
initiated.
7-0
PVH2
R
X
Program verify row switch time in half-microseconds.
744
Device Configuration
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated