Texas Instruments CC2650DK ユーザーズマニュアル
Factory Configuration (FCFG)
9.2.1.75 PWD_CURR_65C Register (Offset = 3A8h) [reset = 1C259C14h]
PWD_CURR_65C is shown in
and described in
Power Down Current Control 65C
Figure 9-96. PWD_CURR_65C Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DELTA_CACHE_REF
DELTA_RFMEM_RET
R-1Ch
R-25h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DELTA_XOSC_LPM
BASELINE
R-9Ch
R-14h
Table 9-98. PWD_CURR_65C Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
DELTA_CACHE_REF
R
1Ch
Additional maximum current, in units of 1uA, with cache retention
23-16
DELTA_RFMEM_RET
R
25h
Additional maximum current, in 1uA units, with RF memory retention
15-8
DELTA_XOSC_LPM
R
9Ch
Additional maximum current, in units of 1uA, with XOSC_HF on in
low-power mode
low-power mode
7-0
BASELINE
R
14h
Worst-case baseline maximum powerdown current, in units of 0.5uA
792
Device Configuration
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated