Texas Instruments CC2650DK ユーザーズマニュアル
AES Cryptoprocessor Overview
10.1.1.1 Debug Capabilities
The AES module provides the following status registers to monitor operations of the engine:
•
DMA status and port-error status registers
•
Interrupt status registers in the master control module
•
Key-store module status register
10.1.1.2 Exception Handling
The AES module can detect AHB master bus errors and abort the DMA operation. The AES key-store
module can detect key-load errors and does not store the bad key in that case. In both cases, the status
register in the master-control module indicates the error.
module can detect key-load errors and does not store the bad key in that case. In both cases, the status
register in the master-control module indicates the error.
10.1.2 Power Management and Sleep Modes
To save power, the application can disable the clock to the AES module when not in use. The AES is
clock-gated in sleep mode by setting the CRYPTO_CLK_EN bit in the [SECDMACLKGS] register. The
AES can also be clock-gated in run mode by setting the CRYPTO_CLK_EN bit in the [SECDMACLKGR]
register.
clock-gated in sleep mode by setting the CRYPTO_CLK_EN bit in the [SECDMACLKGS] register. The
AES can also be clock-gated in run mode by setting the CRYPTO_CLK_EN bit in the [SECDMACLKGR]
register.
10.1.3 Hardware Description
10.1.3.1 AHB Slave Bus
Internal registers of the AES module are accessed by the slave interface. The AHB slave interface
accepts 8, 16, and 32-bit transfers. However, the AES module only accepts 32-bit single access.
accepts 8, 16, and 32-bit transfers. However, the AES module only accepts 32-bit single access.
As each transfer is checked for multiple error conditions depending on the address, size, and type of the
transfer, these checks are performed on registered signals to improve timing on the input signals.
Therefore, one wait cycle must be inserted for each transfer. If an ERROR response occurs, h_ready_out
must be taken low one cycle after reception of the address. This results in the following timing:
transfer, these checks are performed on registered signals to improve timing on the input signals.
Therefore, one wait cycle must be inserted for each transfer. If an ERROR response occurs, h_ready_out
must be taken low one cycle after reception of the address. This results in the following timing:
•
Write transfers take 2 clock cycles
•
Read transfers take 3 clock cycles
The AHB slave handles only the little endian transfers and for register access, only 32-bit single accesses
are allowed.
are allowed.
10.1.3.2 AHB Master Bus
The module is configured by the DMA configuration [DMABUSCFG] register (refer to , DMAC Master Run-
Time Parameters) and performs single 8-bit or 32-bit non-sequential single transfers by default. Transfer
addresses and length parameters of the DMA transfer are byte aligned.
Time Parameters) and performs single 8-bit or 32-bit non-sequential single transfers by default. Transfer
addresses and length parameters of the DMA transfer are byte aligned.
When the AES module requests a DMA transfer, the AHB master asserts and signals to indicate to the
arbiter that it requires the bus. This signal stays asserted until the address phase of the last transfer of the
DMA and no new DMA transfers are requested.
arbiter that it requires the bus. This signal stays asserted until the address phase of the last transfer of the
DMA and no new DMA transfers are requested.
When no DMA transfers are requested, the AHB master performs IDLE transfers. If the AHB master is
already granted and gets the DMA request, the first write transfer is an IDLE transfer. The last transfer is
always an IDLE transfer.
already granted and gets the DMA request, the first write transfer is an IDLE transfer. The last transfer is
always an IDLE transfer.
If the AHB_MST1_LOCK_EN bit is asserted, the AHB master asserts a lock signal to indicate the AHB is
performing a number of indivisible transfers. The arbiter does not grant any other AHB master access to
the bus when the first transfer of the sequence of locked transfers has commenced. The AHB master
inserts an IDLE transfer after each block sequence.
performing a number of indivisible transfers. The arbiter does not grant any other AHB master access to
the bus when the first transfer of the sequence of locked transfers has commenced. The AHB master
inserts an IDLE transfer after each block sequence.
The AHB master can handle big and little endian transfers. The AES module is little endian-oriented
internally. However, when connected to a big endian AHB system, a conversion from big to little endian
can be done in the AHB master interface. By default, a little endian-oriented AHB-host system is assumed.
When the AHB system is big endian-oriented, the AHB_MST1_BIGEND must be set to 1.
internally. However, when connected to a big endian AHB system, a conversion from big to little endian
can be done in the AHB master interface. By default, a little endian-oriented AHB-host system is assumed.
When the AHB system is big endian-oriented, the AHB_MST1_BIGEND must be set to 1.
799
SWCU117A – February 2015 – Revised March 2015
Cryptography
Copyright © 2015, Texas Instruments Incorporated