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AES Cryptoprocessor Overview
If the address and lengths are 32-bit aligned, the master does only NONSEQ and SINGLE-type transfers
with a size of 4 bytes.
with a size of 4 bytes.
The DMAC splits channel DMA operation into small DMA transfers. The size of small DMA transfers is
determined by the target internal module, and equals to block size of the cryptographic operation.
determined by the target internal module, and equals to block size of the cryptographic operation.
The DMAC has the following features:
•
Two channels (one inbound and one outbound) that can be enabled at the same time
•
A maximum size of the DMA operation, controlled by 16-bit length register
•
An arbiter to schedule channel accesses to the external AHB port
•
Functionality to capture external bus errors
The DMAC consists of two DMA channels with programmable priority: one is programmable to move input
data and keys from the external memory to the AES module, and another is programmable to move result
data from the AES module to the external memory. Access to the channels of the AHB master port is
handled by the arbiter module.
data and keys from the external memory to the AES module, and another is programmable to move result
data from the AES module to the external memory. Access to the channels of the AHB master port is
handled by the arbiter module.
Channel control registers are used for channel enabling and priority selection. When a channel is
disabled, it becomes inactive only when all ongoing requests are finished.
disabled, it becomes inactive only when all ongoing requests are finished.
NOTE:
All [DMACHxCTL], [DMACHxEXTADDR], and [DMACHxLEN] channel control registers must
be programmed by the host to start a new DMA operation.
The DMAC transfers data between a source address and destination address. Starting at a non-word
aligned boundary, byte transfers are generated until a word boundary is reached. From then onwards,
word transfers are generated as long as data is available. If the transfer does not finish on word-aligned
address, the remaining transfers are again byte transfers.
aligned boundary, byte transfers are generated until a word boundary is reached. From then onwards,
word transfers are generated as long as data is available. If the transfer does not finish on word-aligned
address, the remaining transfers are again byte transfers.
NOTE:
No half word transfers are generated.
When the AHB_MST1_INCR_EN bit is set to 1, defined length bursts and single-transfers are generated
by default. The maximum size depends on the programmed burst size.
by default. The maximum size depends on the programmed burst size.
The DMA controller (DMAC) registers are mapped to the external register map. To start the operation, the
host must program the mode of the DMAC and parameters of the operation. These parameters involve
direction (read, write, or read-and-write), length (1-65535 bytes), external source address (for reading),
and external destination address (for writing). For details of the registers, refer to the end of this chapter.
host must program the mode of the DMAC and parameters of the operation. These parameters involve
direction (read, write, or read-and-write), length (1-65535 bytes), external source address (for reading),
and external destination address (for writing). For details of the registers, refer to the end of this chapter.
NOTE:
The internal destination is programmed using a dedicated algorithm selection register in
master control module. The burst size is provided to the DMAC based on the setting of that
register.
register.
10.1.4.3.1 Internal Operation
The DMAC operates in conjunction with the AHB master adapter that has two ports. One is an external
AHB port used to perform read and write operations to the external AHB subsystem. This port can
address the complete 32-bit address range. The second one is an internal TCM port (master TCM) used
to perform read and write operations to the internal modules of the crypto core AES engine and Key store.
Assignment of the internal modules for DMA operation must be selected in the master control module
(refer to
AHB port used to perform read and write operations to the external AHB subsystem. This port can
address the complete 32-bit address range. The second one is an internal TCM port (master TCM) used
to perform read and write operations to the internal modules of the crypto core AES engine and Key store.
Assignment of the internal modules for DMA operation must be selected in the master control module
(refer to
, Algorithm Select); therefore an internal address is not needed in the DMAC.
The data path from the TCM port of the AHB master module to the internal modules is located outside of
the DMAC. The DMAC only observes the number of transferred words to determine when the requested
DMA operation is finished for the corresponding channel.
the DMAC. The DMAC only observes the number of transferred words to determine when the requested
DMA operation is finished for the corresponding channel.
The key store is a 32-bit block memory with a depth of 32 words, surrounded by control logic. When the
AES module is configured to write keys to this module via DMA, the key store internally manages access
to the key store RAM based on its register settings (including generation of the key store RAM addresses).
The AES module supports only DMA write operations to the key store.
AES module is configured to write keys to this module via DMA, the key store internally manages access
to the key store RAM based on its register settings (including generation of the key store RAM addresses).
The AES module supports only DMA write operations to the key store.
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SWCU117A – February 2015 – Revised March 2015
Cryptography
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