Texas Instruments CC2650DK ユーザーズマニュアル
Cortex-M3 Processor Registers
2.7.1.37 LSR Register (Offset = FB4h) [reset = X]
LSR is shown in
and described in
Lock Status Use this register to enable write accesses to the Control Register.
Figure 2-40. LSR Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
BYTEACC
ACCESS
PRESENT
R-X
R-X
R-1h
R-1h
Table 2-63. LSR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-3
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
BYTEACC
R
X
Reads 0 which means 8-bit lock access is not be implemented.
1
ACCESS
R
1h
Write access to component is blocked. All writes are ignored, reads
are permitted.
are permitted.
0
PRESENT
R
1h
Indicates that a lock mechanism exists for this component.
90
SWCU117A – February 2015 – Revised March 2015
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