Microchip Technology MCP23X17EV データシート
© 2006 Microchip Technology Inc.
DS01043A-page 3
AN1043
INTERRUPT FEATURES
The MCP23X08 has one interrupt pin and the
MCP23X17 has two interrupt pins.
For the MCP23X17, each interrupt pin is associated
with an 8-bit port. INTA is associated with Port A and
INTB is associated with Port B.
MCP23X17 has two interrupt pins.
For the MCP23X17, each interrupt pin is associated
with an 8-bit port. INTA is associated with Port A and
INTB is associated with Port B.
Interrupt Mapping
The MCP23X17 interrupt pins can be mapped in two
ways (see Figure 2) as controlled by IOCON.MIRROR:
1.
ways (see Figure 2) as controlled by IOCON.MIRROR:
1.
Interrupt pins operate independently. INTA
reflects interrupt conditions on Port A and INTB
reflects interrupt conditions on Port B.
reflects interrupt conditions on Port A and INTB
reflects interrupt conditions on Port B.
2.
Both interrupt pins go active when an interrupt
occurs on either port.
occurs on either port.
Interrupt Polarity and Open-Drain
The interrupts can be configured to operate in three
modes:
1.
modes:
1.
Active-High.
2.
Active-Low.
3.
Open-Drain.
The interrupt polarity and open-drain is configured via
INTPOL and ODR bits in the IOCON register.
INTPOL and ODR bits in the IOCON register.
Interrupt Conditions
There are several configurable interrupt conditions
which allow flexible configurations.
which allow flexible configurations.
INTERRUPT-ON-PIN-CHANGE
Pins configured for interrupt-on-pin-change will
cause an interrupt to occur if a pin changes to the
opposite state. The default state is reset after an
interrupt is serviced. For example, an interrupt occurs
by an input changing from 1 to 0. The interrupt is then
serviced while the pin state is still 0 by reading GPIO or
INTCAP register. The new initial state for the pin is a
logic 0. Likewise, if the pin is toggled back to a logic 1
before servicing the interrupt, the new default state is a
logic 1.
The interrupt condition is cleared by reading either
INTCAP or GPIO register. The new pin state default is
set when the interrupt is cleared.
cause an interrupt to occur if a pin changes to the
opposite state. The default state is reset after an
interrupt is serviced. For example, an interrupt occurs
by an input changing from 1 to 0. The interrupt is then
serviced while the pin state is still 0 by reading GPIO or
INTCAP register. The new initial state for the pin is a
logic 0. Likewise, if the pin is toggled back to a logic 1
before servicing the interrupt, the new default state is a
logic 1.
The interrupt condition is cleared by reading either
INTCAP or GPIO register. The new pin state default is
set when the interrupt is cleared.
INTERRUPT-ON-CHANGE FROM DEFVAL
REGISTER VALUE
REGISTER VALUE
Pins configured for interrupt-on-change from
register value will cause an interrupt to occur if the
corresponding input pin differs from the register bit. The
interrupt condition will remain as long as the condition
exists, regardless if the INTCAP or GPIO is read.
For example, if DEFVAL<b0> = 0. An interrupt will
occur if the pin changes to a logic 1 and the interrupt
will remain as long as the pin remains a logic 1. The
interrupt condition will clear if the pin changes back to
a logic 0 and INTCAP or GPIO is read.
register value will cause an interrupt to occur if the
corresponding input pin differs from the register bit. The
interrupt condition will remain as long as the condition
exists, regardless if the INTCAP or GPIO is read.
For example, if DEFVAL<b0> = 0. An interrupt will
occur if the pin changes to a logic 1 and the interrupt
will remain as long as the pin remains a logic 1. The
interrupt condition will clear if the pin changes back to
a logic 0 and INTCAP or GPIO is read.
FIGURE 2:
INTERRUPT BLOCK DIAGRAM
Note:
For the MCP23X17, the polarity and open-
drain configuration of the INTA and INTB
pins are not independent. Both pins are
configured the same.
drain configuration of the INTA and INTB
pins are not independent. Both pins are
configured the same.
Polarity
Control
INTA
INTB
Open-
Drain
Control
A
B
0
1
0
1
IOCON.MIRROR
IOCON.INTPOL
IOCON.ODR