Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 435
PIC18F87J72 FAMILY
FIGURE B-1:
DUAL-CHANNEL AFE FUNCTIONAL BLOCK DIAGRAM
CH0+
CH0-
CH1+
CH1-
SDOA
SDIA
SCKA
SCKA
DUAL-DS ADC
Digital
SINC
3
-
+
PGA
MCLK
CLKIA
DR
ARESET
Digital SPI
Interface
Clock
Generation
SINC
3
-
+
PGA
Modulator
AMCLK
DMCLK/DRCLK
DMCLK
Phase
Shifter
PHASE<7:0>
OSR<1:0>
PRE<1:0>
DATA_CH0<23:0>
DATA_CH1<23:0>
CSA
REFIN+/OUT+
REFIN-
SAV
DD
SAV
SS
SV
SS
SV
DD
POR
AV
DD
Monitoring
POR
Modulator
V
REF
+
V
REF
-
VREFEXT
Voltage
Reference
V
REF
+
-
D-S
D-S
F
SDN<1:0>, RESET<1:0>, GAIN<7:0>
Analog