Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 437
PIC18F87J72 FAMILY
The Data Ready pin is independent of the SPI interface
and acts like an interrupt output. The pin state is not
latched and the pulse width (and period) are both deter-
mined by the MCLK frequency, oversampling rate and
internal clock prescale settings. The DR pulse width is
equal to one DMCLK period and the frequency of the
pulses is equal to DRCLK (see Figure 29-22 in
Section 29.0 “Electrical Characteristics” of the data
sheet).
and acts like an interrupt output. The pin state is not
latched and the pulse width (and period) are both deter-
mined by the MCLK frequency, oversampling rate and
internal clock prescale settings. The DR pulse width is
equal to one DMCLK period and the frequency of the
pulses is equal to DRCLK (see Figure 29-22 in
Section 29.0 “Electrical Characteristics” of the data
sheet).
B.2.10
MASTER CLOCK INPUT (CLKIA)
CLKIA provides the master clock for the device. The
typical clock frequency specified is 4 MHz. However,
the clock frequency can be 1 MHz to 5 MHz without
disturbing ADC accuracy. With the current boost circuit
enabled, the master clock can be used up to
8.192 MHz without disturbing ADC accuracy. Appropri-
ate load capacitance should be connected to these
pins for proper operation.
typical clock frequency specified is 4 MHz. However,
the clock frequency can be 1 MHz to 5 MHz without
disturbing ADC accuracy. With the current boost circuit
enabled, the master clock can be used up to
8.192 MHz without disturbing ADC accuracy. Appropri-
ate load capacitance should be connected to these
pins for proper operation.
B.2.11
CHIP SELECT (CSA)
This pin is the SPI chip select that enables the serial
communication. When this pin is high, no
communication can take place. A chip select falling
edge initiates the serial communication and a chip
select rising edge terminates the communication. No
communication can take place even when CSA is low
and when ARESET is low.
This input is Schmitt triggered.
communication. When this pin is high, no
communication can take place. A chip select falling
edge initiates the serial communication and a chip
select rising edge terminates the communication. No
communication can take place even when CSA is low
and when ARESET is low.
This input is Schmitt triggered.
B.2.12
SERIAL DATA CLOCK (SCKA)
This is the serial clock pin for SPI communication.
Data is clocked into the device on the rising edge of
SCK. Data is clocked out of the device on the falling
edge of SCK.
The AFE interface is compatible with both SPI 0,0 and
1,1 modes. SPI modes can only be changed during a
Reset.
The maximum clock speed specified is 20 MHz when
SV
Data is clocked into the device on the rising edge of
SCK. Data is clocked out of the device on the falling
edge of SCK.
The AFE interface is compatible with both SPI 0,0 and
1,1 modes. SPI modes can only be changed during a
Reset.
The maximum clock speed specified is 20 MHz when
SV
DD
> 4.5V and 10 MHz otherwise.
This input is Schmitt triggered.
B.2.13
SERIAL DATA OUTPUT (SDOA)
This is the SPI data output pin. Data is clocked out of
the device on the falling edge of SCK.
This pin stays high impedance during the first command
byte. It also stays high impedance during the whole com-
munication for write commands and when the CSA pin
is high or when the ARESET pin is low. This pin is active
only when a read command is processed. Each read is
processed by a packet of 8 bits.
the device on the falling edge of SCK.
This pin stays high impedance during the first command
byte. It also stays high impedance during the whole com-
munication for write commands and when the CSA pin
is high or when the ARESET pin is low. This pin is active
only when a read command is processed. Each read is
processed by a packet of 8 bits.
B.2.14
SERIAL DATA INPUT (SDIA)
This is the SPI data input pin. Data is clocked into the
device on the rising edge of SCK.
When CS is low, this pin is used to communicate with
series of 8-bit commands.
The interface is half-duplex (inputs and outputs do not
happen at the same time).
Each communication starts with a chip select falling
edge, followed by an 8-bit command word entered
through the SDI pin. Each command is either a read or
a write command. Toggling SDI during a read
command has no effect.
This input is Schmitt triggered.
device on the rising edge of SCK.
When CS is low, this pin is used to communicate with
series of 8-bit commands.
The interface is half-duplex (inputs and outputs do not
happen at the same time).
Each communication starts with a chip select falling
edge, followed by an 8-bit command word entered
through the SDI pin. Each command is either a read or
a write command. Toggling SDI during a read
command has no effect.
This input is Schmitt triggered.
Note:
This pin should not be left floating when the
DR_HIZN bit is low; a 10 k
DR_HIZN bit is low; a 10 k
pull-up resistor
connected to DV
DD
is recommended.