Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 439
PIC18F87J72 FAMILY
B.3.5
OSR – OVERSAMPLING RATIO
The ratio of the sampling frequency to the output data
rate, OSR = DMCLK/DRCLK. The default OSR is 64, or
with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz,
f
rate, OSR = DMCLK/DRCLK. The default OSR is 64, or
with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz,
f
S
= 1 MHz, f
D
= 15.625 ksps. The following bits in the
CONFIG1 register are used to change the oversampling
ratio (OSR).
ratio (OSR).
B.3.6
OFFSET ERROR
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. This offset error can easily be calibrated out by
a MCU with a subtraction. The offset is specified in mV.
The offset on the dual-channel AFE has a low
temperature coefficient.
are shorted together (VIN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. This offset error can easily be calibrated out by
a MCU with a subtraction. The offset is specified in mV.
The offset on the dual-channel AFE has a low
temperature coefficient.
B.3.7
GAIN ERROR
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in per-
cent compared to the ideal transfer function defined by
Equation B-15. The specification incorporates both
PGA and ADC gain error contributions, but not the
V
transfer function. It is the deviation expressed in per-
cent compared to the ideal transfer function defined by
Equation B-15. The specification incorporates both
PGA and ADC gain error contributions, but not the
V
REF
contribution (it is measured with an external
V
REF
).This error varies with PGA and OSR settings.
The gain error of the dual-channel AFE has a low
temperature coefficient.
temperature coefficient.
B.3.8
INTEGRAL NON-LINEARITY ERROR
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the endpoints equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the endpoints equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
B.3.9
SIGNAL-TO-NOISE RATIO (SNR)
For the AFE, the signal-to-noise ratio is a ratio of the
output fundamental signal power to the noise power
(not including the harmonics of the signal), when the
input is a sine wave at a predetermined frequency. It is
measured in dB. Usually, only the maximum signal to
noise ratio is specified. The SNR figure depends mainly
on the OSR and DITHER settings of the device.
output fundamental signal power to the noise power
(not including the harmonics of the signal), when the
input is a sine wave at a predetermined frequency. It is
measured in dB. Usually, only the maximum signal to
noise ratio is specified. The SNR figure depends mainly
on the OSR and DITHER settings of the device.
TABLE B-2:
DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE
PRE<1:0>
OSR<1:0>
OSR
AMCLK
DMCLK
DRCLK
DRCLK
(ksps)
SINAD
(dB)
ENOB
(bits)
1
1
1
1
256
MCLK/8
MCLK/32
MCLK/8192
0.4882
91.4
14.89
1
1
1
0
128
MCLK/8
MCLK/32
MCLK/4096
0.976
86.6
14.10
1
1
0
1
64
MCLK/8
MCLK/32
MCLK/2048
1.95
78.7
12.78
1
1
0
0
32
MCLK/8
MCLK/32
MCLK/1024
3.9
68.2
11.04
1
0
1
1
256
MCLK/4
MCLK/16
MCLK/4096
0.976
91.4
14.89
1
0
1
0
128
MCLK/4
MCLK/16
MCLK/2048
1.95
86.6
14.10
1
0
0
1
64
MCLK/4
MCLK/16
MCLK/1024
3.9
78.7
12.78
1
0
0
0
32
MCLK/4
MCLK/16
MCLK/512
7.8125
68.2
11.04
0
1
1
1
256
MCLK/2
MCLK/8
MCLK/2048
1.95
91.4
14.89
0
1
1
0
128
MCLK/2
MCLK/8
MCLK/1024
3.9
86.6
14.10
0
1
0
1
64
MCLK/2
MCLK/8
MCLK/512
7.8125
78.7
12.78
0
1
0
0
32
MCLK/2
MCLK/8
MCLK/256
15.625
68.2
11.04
0
0
1
1
256
MCLK
MCLK/4
MCLK/1024
3.9
91.4
14.89
0
0
1
0
128
MCLK
MCLK/4
MCLK/512
7.8125
86.6
14.10
0
0
0
1
64
MCLK
MCLK/4
MCLK/256
15.625
78.7
12.78
0
0
0
0
32
MCLK
MCLK/4
MCLK/128
31.25
68.2
11.04
Note:
For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.
TABLE B-3:
OVERSAMPLING RATIO
SETTINGS
SETTINGS
CONFIG
OVERSAMPLING RATIO
(OSR)
OSR<1:0>
0
0
32
0
1
64 (default)
1
0
128
1
1
256