Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 88
Preliminary
2010 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
MULTIPLICATION
ALGORITHM
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4:
16 x 16 SIGNED MULTIPLY
ROUTINE
ROUTINE
RES3:RES0
=
ARG1H:ARG1L
ARG2H:ARG2L
=
(ARG1H
ARG2H 2
16
) +
(ARG1H
ARG2L 2
8
) +
(ARG1L
ARG2H 2
8
) +
(ARG1L
ARG2L)
MOVF
ARG1L, W
MULWF
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
; PRODH:PRODL
MOVFF
PRODH, RES1
;
MOVFF
PRODL, RES0
;
;
MOVF
ARG1H, W
MULWF
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
; PRODH:PRODL
MOVFF
PRODH, RES3
;
MOVFF
PRODL, RES2
;
;
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1, F
; Add cross
MOVF
PRODH, W
; products
ADDWFC RES2, F
;
CLRF
WREG
;
ADDWFC RES3, F
;
;
MOVF
ARG1H, W
;
MULWF
ARG2L
; ARG1H * ARG2L->
; PRODH:PRODL
; PRODH:PRODL
MOVF
PRODL, W
;
ADDWF
RES1, F
; Add cross
MOVF
PRODH, W
; products
ADDWFC RES2, F
;
CLRF
WREG
;
ADDWFC RES3, F
;
RES3:RES0=
ARG1H:ARG1L
ARG2H:ARG2L
=
(ARG1H
ARG2H 2
16
) +
(ARG1H
ARG2L 2
8
) +
(ARG1L
ARG2H 2
8
) +
(ARG1L
ARG2L) +
(-1
ARG2H<7> ARG1H:ARG1L 2
16
) +
(-1
ARG1H<7> ARG2H:ARG2L 2
16
)
MOVF ARG1L, W
MULWFARG2L
MULWFARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
; PRODH:PRODL
MOVFFPRODH, RES1 ;
MOVFFPRODL, RES0 ;
MOVFFPRODL, RES0 ;
;
MOVF ARG1H, W
MULWFARG2H
MULWFARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
; PRODH:PRODL
MOVFFPRODH, RES3 ;
MOVFFPRODL, RES2 ;
MOVFFPRODL, RES2 ;
;
MOVF ARG1L, W
MULWFARG2H
MULWFARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
; PRODH:PRODL
MOVF PRODL, W
;
ADDWFRES1, F
; Add cross
MOVF PRODH, W
; products
ADDWFCRES2, F
;
CLRF WREG
;
ADDWFCRES3, F
;
;
MOVF ARG1H, W
;
MULWFARG2L
; ARG1H * ARG2L ->
; PRODH:PRODL
; PRODH:PRODL
MOVF PRODL, W
;
ADDWFRES1, F
; Add cross
MOVF PRODH, W
; products
ADDWFC RES2, F
;
CLRF WREG
;
ADDWFCRES3, F
;
;
BTFSSARG2H, 7
; ARG2H:ARG2L neg?
BRA
SIGN_ARG1
; no, check ARG1
MOVF ARG1L, W
;
SUBWFRES2
;
MOVF ARG1H, W
;
SUBWFBRES3
;
SIGN_ARG1
SIGN_ARG1
BTFSSARG1H, 7
; ARG1H:ARG1L neg?
BRA
CONT_CODE
; no, done
MOVF ARG2L, W
;
SUBWFRES2
;
MOVF ARG2H, W
;
SUBWFBRES3
;
CONT_CODE
:
CONT_CODE
: