Microchip Technology ARD00330 データシート

Microchip Technology

PIC18F87J72 FAMILY

DS39979A-page 90

Preliminary

 2010 Microchip Technology Inc.

FIGURE 9-1:

PIC18F87J72 FAMILY INTERRUPT LOGIC

TMR0IE

GIE/GIEH

PEIE/GIEL

Wake-up if in

Interrupt to CPU
Vector to Location
0008h

INT2IF

INT2IE
INT2IP

INT1IF

INT1IE
INT1IP

TMR0IF

TMR0IE
TMR0IP

RBIF

RBIE
RBIP

IPEN

TMR0IF

TMR0IP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

PEIE/GIEL

Interrupt to CPU

Vector to Location

IPEN

IPEN

0018h

PIR1<6:3,1:0>

PIE1<6:3,1:0>

IPR1<6:3,1:0>

High-Priority Interrupt Generation

Low-Priority Interrupt Generation

Idle or Sleep modes

GIE/GIEH

INT3IF

INT3IE

INT3IP

INT3IF

INT3IE
INT3IP

PIR2<7:6,3:1>

PIE2<7:6 3:1>

IPR2<7:6,3:1>

PIR3<6:0>

PIE3<6:0>

IPR3<6:0>

PIR1<6:3,1:0>
PIE1<6:3,1:0>
IPR1<6:3,1:0>

PIR2<7:6,3:1>
PIE2<7:6,3:1>
IPR2<7:6,3:1>

PIR3<6:0>
PIE3<6:0>
IPR3<6:0>

IPEN