Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 426
Preliminary
2010 Microchip Technology Inc.
TABLE 29-27: DUAL-CHANNEL AFE SERIAL PERIPHERAL INTERFACE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at SAV
DD
= 4.5 to 5.5V,
DV
DD
= 2.7 to 5.5V, -40°C < T
A
<+85°C, C
LOAD
= 30 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Serial Clock Frequency
f
SCK
—
—
—
—
—
—
20
10
10
MHz
MHz
MHz
4.5
SV
DD
5.5
2.7
SV
DD
5.5
CS Setup Time
t
CSS
25
50
50
—
—
—
—
—
—
ns
ns
ns
4.5
SV
DD
5.5
2.7
SV
DD
5.5
CS Hold Time
t
CSH
50
100
—
—
—
—
—
—
ns
ns
ns
4.5
SV
DD
5.5
2.7
SV
DD
5.5
CS Disable Time
t
CSD
50
—
—
ns
—
Data Setup Time
t
SU
5
10
—
—
—
—
—
—
ns
ns
ns
4.5
SV
DD
5.5
2.7
SV
DD
5.5
Data Hold Time
t
HD
10
20
20
—
—
—
—
—
—
ns
ns
ns
4.5
SV
DD
5.5
2.7
SV
DD
5.5
Serial Clock High Time
t
HI
25
50
50
—
—
—
—
—
—
ns
ns
ns
4.5
SV
DD
5.5
2.7
SV
DD
5.5
Serial Clock Low Time
t
LO
25
50
50
—
—
—
—
—
—
ns
ns
ns
4.5
DV
DD
5.5
2.7
DV
DD
5.5
Serial Clock Delay Time
t
CLD
50
—
—
ns
Serial Clock Enable Time
t
CLE
50
—
—
ns
Output Valid from SCK Low
t
DO
—
—
50
ns
2.7
SV
DD
5.5
Output hold time
t
HO
0
—
—
ns
Output disable time
t
DIS
—
—
—
—
—
—
25
50
50
ns
ns
ns
4.5
SV
DD
5.5
2.7
SV
DD
5.5 (Note 1)
Reset Pulse Width (RESET)
t
MCLR
100
—
—
ns
2.7
SV
DD
5.5
Data Transfer Time to DR (Data Ready) t
DODR
—
—
50
ns
2.7
SV
DD
5.5
Data Ready Pulse Low Time
t
DRP
—
1/DMCLK
—
µs
2.7
SV
DD
5.5
Schmitt Trigger High-Level Input
Voltage
Voltage
V
IH
1
0.7 SV
DD
—
SV
DD
+ 1
V
Schmitt Trigger Low-Level Input Voltage
V
IL
1
-0.3
—
0.2 SV
DD
V
Hysteresis of Schmitt Trigger Inputs
(all digital inputs)
(all digital inputs)
V
HYS
300
—
—
mV
Low-Level Output Voltage, SDOA Pin
V
OL
—
—
0.4
V
I
OL
= +2.5 mA, SV
DD
= 5.0V
Low-Level Output Voltage, DR Pin
V
OL
—
0.4
V
I
OL
= +1.25 mA, SV
DD
= 5.0V
High-Level Output Voltage, SDOA Pin
V
OH
SV
DD
– 0.5
—
—
V
I
OH
= -2.5 mA, SV
DD
= 5.0V
High-Level Output Voltage, DR Pin
V
OH
SV
DD
– 0.5
—
—
V
I
OH
= -1.25 mA, SV
DD
= 5.0V
Input Leakage Current
I
LI
—
—
±1
µA
CSA = SV
DD
, V
IN
= SV
SS
or SV
DD
Output Leakage Current
I
LO
—
—
±1
µA
CSA = SV
DD
, V
OUT
= SV
SS
or SV
DD
Internal Capacitance (all inputs and
outputs)
outputs)
C
INT
—
—
7
pF
T
A
= 25°C,
SCKA = 1.0 MHz,
SV
SV
DD
= 5.0V (Note 1)
Note 1:
This parameter is periodically sampled and is not 100% tested.