Microchip Technology MA240029 データシート
2010-2011 Microchip Technology Inc.
DS39996F-page 145
PIC24FJ128GA310 FAMILY
9.0
OSCILLATOR
CONFIGURATION
CONFIGURATION
The oscillator system for PIC24FJ128GA310 family
devices has the following features:
• A total of four external and internal oscillator options
devices has the following features:
• A total of four external and internal oscillator options
as clock sources, providing 11 different clock modes
• On-chip 4x PLL to boost internal operating frequency
on select internal and external oscillator sources
• Software-controllable switching between various
clock sources
• Software-controllable postscaler for selective
clocking of CPU for system power savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
or shutdown
• A separate and independently configurable system
clock output for synchronizing external hardware
.
FIGURE 9-1:
PIC24FJ128GA310 FAMILY CLOCK DIAGRAM
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”
,
“Section 6. Oscillator”
(DS39700).
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCO
SOSCI
Clock Source Option
for Other Modules
for Other Modules
OSCI
OSCO
Primary Oscillator
XT, HS, EC
P
ostscale
r
CLKDIV<10:8>
WDT, PWRT
8 MHz
FRCDIV
31 kHz (nominal)
FRC
Oscillator
LPRC
Oscillator
SOSC
LPRC
Clock Control Logic
Fail-Safe
Clock
Monitor
FRC
(nominal)
4 x PLL
8 MHz
4 MHz
4 MHz
CPU
Peripherals
P
ostscale
r
CLKDIV<14:12>
CLKO
Reference Clock
Generator
REFO
REFOCON<15:8>
XTPLL, HSPLL,
ECPLL, FRCPLL