Microchip Technology MA240029 マニュアル

目次

• Extreme Low-Power Features:

  1
• Peripheral Features:

  1
• Peripheral Features (continued):

  1
• Analog Features:

  1
• High-Performance CPU:

  2
• Special Microcontroller Features:

  2
• Pin Diagrams

  3
• Pin Diagrams (continued)

  4
• Pin Diagrams (continued)

  5
• Pin Diagrams (continued)

  6
• Table of Contents

  9
• Most Current Data Sheet

  10
• Errata

  10
• Customer Notification System

  10
• 1.0 Device Overview

  11
  • 1.1 Core Features

    11
    • 1.1.1 16-Bit Architecture

      11
    • 1.1.2 nanoWatt XLP Power-Saving Technology

      11
    • 1.1.3 Oscillator Options and Features

      11
    • 1.1.4 Easy Migration

      11
  • 1.2 DMA Controller

    12
  • 1.3 LCD Controller

    12
  • 1.4 Other Special Features

    12
  • 1.5 Details on Individual Family Members

    12
    • TABLE 1-1: Device Features for the PIC24FJ128GA310 family: 64-pin

      13
    • TABLE 1-2: Device Features for the PIC24FJ128GA310 family: 80-pin

      14
    • TABLE 1-3: Device Features for the PIC24FJ128GA310 family: 100-pin Devices

      15
    • FIGURE 1-1: PIC24FJ128GA310 family General Block Diagram

      16
    • TABLE 1-4: PIC24FJ128GA310 family Pinout Descriptions

      17
• 2.0 Guidelines for Getting Started with 16-bit Microcontrollers

  29
  • 2.1 Basic Connection Requirements

    29
    • FIGURE 2-1: Recommended Minimum connections

      29
  • 2.2 Power Supply Pins

    30
    • 2.2.1 Decoupling Capacitors

      30
    • 2.2.2 Tank Capacitors

      30
  • 2.3 Master Clear (MCLR) Pin

    30
    • FIGURE 2-2: Example of MCLR Pin Connections

      30
  • 2.4 Voltage Regulator Pin (Vcap)

    31
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      31
    • TABLE 2-1: Suitable Capacitor Equivalents

      31
    • 2.4.1 Considerations for Ceramic Capacitors

      32
      • FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics

        32
  • 2.5 ICSP Pins

    32
  • 2.6 External Oscillator Pins

    33
    • FIGURE 2-5: Suggested Placement of the Oscillator Circuit

      33
  • 2.7 Configuration of Analog and Digital Pins During ICSP Operations

    34
  • 2.8 Unused I/Os

    34
• 3.0 CPU

  35
  • 3.1 Programmer’s Model

    35
    • FIGURE 3-1: PIC24F CPU Core Block Diagram

      36
    • TABLE 3-1: CPU Core Registers

      36
    • FIGURE 3-2: Programmer’s Model

      37
  • 3.2 CPU Control Registers

    38
    • Register 3-1: SR: ALU STATUS Register

      38
    • Register 3-2: CORCON: CPU Core Control Register

      39
  • 3.3 Arithmetic Logic Unit (ALU)

    40
    • 3.3.1 Multiplier

      40
    • 3.3.2 Divider

      40
    • 3.3.3 Multi-Bit Shift Support

      40
      • TABLE 3-2: Instructions that Use the Single Bit and Multi-Bit Shift Operation

        40
• 4.0 Memory Organization

  41
  • 4.1 Program Memory Space

    41
    • FIGURE 4-1: Program Space Memory Map for PIC24FJ128GA310 family Devices

      41
    • 4.1.1 Program Memory Organization

      42
    • 4.1.2 Hard Memory Vectors

      42
    • 4.1.3 Flash Configuration Words

      42
      • TABLE 4-1: Flash Configuration Words for PIC24FJ128GA310 family Devices

        42
      • FIGURE 4-2: Program Memory Organization

        42
  • 4.2 Data Memory Space

    43
    • 4.2.1 Data Space Width

      43
      • FIGURE 4-3: Data Space Memory Map for PIC24FJ128GA310 family Devices

        43
    • 4.2.2 Data Memory Organization and Alignment

      44
    • 4.2.3 Near Data Space

      44
    • 4.2.4 Special Function Register (SFR) Space

      44
      • TABLE 4-2: Implemented Regions of SFR Data Space

        44
      • TABLE 4-3: CPU CORE Registers Map

        45
      • TABLE 4-4: ICN Register Map

        46
      • TABLE 4-5: Interrupt Controller Register Map

        47
      • TABLE 4-6: Timer Register Map

        48
      • TABLE 4-7: Input Capture Register Map

        49
      • TABLE 4-8: Output Compare Register Map

        50
      • TABLE 4-9: I2C™ Register Map

        51
      • TABLE 4-10: UART Register Maps

        52
      • TABLE 4-11: SPI Register Map

        53
      • TABLE 4-12: PORTA Register Map(1)

        53
      • TABLE 4-13: PORTb Register Map

        53
      • TABLE 4-14: PORTC Register Map

        54
      • TABLE 4-15: PORTD Register Map

        54
      • TABLE 4-16: PORTE Register Map

        54
      • TABLE 4-17: PORTF Register Map

        55
      • TABLE 4-18: PORTG Register Map

        55
      • TABLE 4-19: Pad Configuration Register Map (PADCFG1)

        55
      • TABLE 4-20: A/D Register Map

        56
      • TABLE 4-21: CTMU Register Map

        57
      • TABLE 4-22: Analog Configuration Register Map

        57
      • TABLE 4-23: DMA Register Map

        58
      • TABLE 4-24: LCD Register Map

        59
      • TABLE 4-25: Parallel Master/Slave Port Register Map

        60
      • TABLE 4-26: Real-Time Clock and Calendar (RTCC) Register Map

        61
      • TABLE 4-27: Data Signal Modulator (DSM) Register Map

        61
      • TABLE 4-28: Comparators Register Map

        61
      • TABLE 4-29: CRC Register Map

        62
      • TABLE 4-30: Peripheral Pin Select Register Map

        62
      • TABLE 4-31: System Control (Clock and Reset) Register Map

        63
      • TABLE 4-32: Deep Sleep Register Map

        64
      • TABLE 4-33: NVM Register Map

        64
      • TABLE 4-34: PMD Register Map

        64
    • 4.2.5 Extended Data Space (EDS)

      65
      • TABLE 4-35: Total Accessible Data Memory

        65
      • FIGURE 4-4: Extended Data Space

        65
      • FIGURE 4-5: EDS Address Generation for Read Operations

        66
      • EXAMPLE 4-1: EDS Read Code In Assembly

        66
      • FIGURE 4-6: EDS Address Generation for Write Operations

        67
      • EXAMPLE 4-2: EDS Write Code In Assembly

        67
      • TABLE 4-36: EDS Memory Address with Different Pages and Addresses

        68
    • 4.2.6 Software Stack

      68
      • FIGURE 4-7: CALL Stack Frame

        68
  • 4.3 Interfacing Program and Data Memory Spaces

    69
    • 4.3.1 Addressing Program Space

      69
      • TABLE 4-37: Program Space Address Construction

        69
      • FIGURE 4-8: Data Access from Program Space Address Generation

        70
    • 4.3.2 Data Access from Program Memory Using Table Instructions

      71
      • FIGURE 4-9: Accessing Program Memory with Table Instructions

        71
    • 4.3.3 Reading Data from Program Memory Using EDS

      72
      • TABLE 4-38: EDS Program Address with different Pages and Addresses

        72
      • EXAMPLE 4-3: EDS Read Code from Program Memory In Assembly

        72
      • FIGURE 4-10: Program Space Visibility Operation to Access Lower Word

        73
      • FIGURE 4-11: Program Space Visibility Operation to Access Upper Word

        73
• 5.0 Direct Memory Access Controller (DMA)

  75
  • FIGURE 5-1: DMA Functional Block Diagram

    75
  • 5.1 Summary of DMA Operations

    76
    • 5.1.1 Source and Destination

      76
    • 5.1.2 Data Size

      76
    • 5.1.3 Trigger Source

      76
    • 5.1.4 Transfer Mode

      76
    • 5.1.5 Addressing Modes

      76
      • FIGURE 5-2: Types of DMA Data Transfers

        77
    • 5.1.6 Channel Priority

      78
  • 5.2 Typical Setup

    78
  • 5.3 Peripheral Module Disable

    78
  • 5.4 Registers

    78
    • Register 5-1: DMACON: DMA Engine Control Register

      79
    • Register 5-2: DMACHn: DMA CHannel n Control Register

      80
    • Register 5-3: DMAINTn: DMA Channel n Interrupt Register

      81
    • TABLE 5-1: DMA Trigger Sources

      82
• 6.0 Flash Program Memory

  83
  • 6.1 Table Instructions and Flash Programming

    83
    • FIGURE 6-1: Addressing for Table Registers

      83
  • 6.2 RTSP Operation

    84
  • 6.3 JTAG Operation

    84
  • 6.4 Enhanced In-Circuit Serial Programming

    84
  • 6.5 Control Registers

    84
  • 6.6 Programming Operations

    84
    • Register 6-1: NVMCON: Flash Memory Control Register

      85
    • 6.6.1 Programming Algorithm for Flash Program Memory

      86
      • EXAMPLE 6-1: Erasing a Program Memory Block (Assembly Language Code)

        86
      • EXAMPLE 6-2: Erasing a Program Memory Block (‘C’ Language Code)

        87
      • EXAMPLE 6-3: LOADING THE WRITE BUFFERS

        87
      • EXAMPLE 6-4: Initiating a Programming Sequence

        87
    • 6.6.2 Programming a single word of flash program memory

      88
      • EXAMPLE 6-5: Programming a Single Word of Flash Program Memory

        88
      • EXAMPLE 6-6: Programming a Single Word of Flash Program Memory (‘C’ Language Code)

        88
• 7.0 Resets

  89
  • FIGURE 7-1: Reset System Block Diagram

    89
  • Register 7-1: RCON: Reset Control Register

    90
  • Register 7-2: RCON2: Reset and System Control Register 2

    92
  • TABLE 7-1: Reset Flag Bit Operation

    93
  • 7.1 Special Function Register Reset States

    93
  • 7.2 Device Reset Times

    93
  • 7.3 Brown-out Reset (BOR)

    93
  • 7.4 Clock Source Selection at Reset

    93
    • TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)

      93
    • TABLE 7-3: Reset Delay Times for Various Device Resets

      94
    • 7.4.1 POR and Long Oscillator Start-up Times

      94
    • 7.4.2 Fail-Safe Clock Monitor (FSCM) and Device Resets

      94
• 8.0 Interrupt Controller

  95
  • 8.1 Interrupt Vector Table

    95
    • 8.1.1 Alternate Interrupt Vector Table

      95
  • 8.2 Reset Sequence

    95
    • FIGURE 8-1: PIC24F Interrupt Vector Table

      96
    • TABLE 8-1: Trap Vector Details

      96
    • TABLE 8-2: Implemented Interrupt Vectors

      97
  • 8.3 Interrupt Control and Status Registers

    98
    • Register 8-1: SR: ALU STATUS Register (in CPU)

      99
    • Register 8-2: CORCON: CPU Control Register

      100
    • Register 8-3: INTCON1: Interrupt Control Register 1

      101
    • Register 8-4: INTCON2: Interrupt Control Register 2

      102
    • Register 8-5: IFS0: Interrupt Flag Status Register 0

      103
    • Register 8-6: IFS1: Interrupt Flag Status Register 1

      105
    • Register 8-7: IFS2: Interrupt Flag Status Register 2

      107
    • Register 8-8: IFS3: Interrupt Flag Status Register 3

      108
    • Register 8-9: IFS4: Interrupt Flag Status Register 4

      109
    • Register 8-10: IFS5: Interrupt Flag Status Register 5

      110
    • Register 8-11: IFS6: Interrupt Flag Status Register 6

      111
    • Register 8-12: IFS7: Interrupt Flag Status Register 7

      111
    • Register 8-13: IEC0: Interrupt Enable Control Register 0

      112
    • Register 8-14: IEC1: Interrupt Enable Control Register 1

      114
    • Register 8-15: IEC2: Interrupt Enable Control Register 2

      116
    • Register 8-16: IEC3: Interrupt Enable Control Register 3

      117
    • Register 8-17: IEC4: Interrupt Enable Control Register 4

      118
    • Register 8-18: IEC5: Interrupt Enable Control Register 5

      119
    • Register 8-19: IEC6: Interrupt Enable Control Register 6

      120
    • Register 8-20: IEC7: Interrupt Enable Control Register 7

      120
    • Register 8-21: IPC0: Interrupt Priority Control Register 0

      121
    • Register 8-22: IPC1: Interrupt Priority Control Register 1

      122
    • Register 8-23: IPC2: Interrupt Priority Control Register 2

      123
    • Register 8-24: IPC3: Interrupt Priority Control Register 3

      124
    • Register 8-25: IPC4: Interrupt Priority Control Register 4

      125
    • Register 8-26: IPC5: Interrupt Priority Control Register 5

      126
    • Register 8-27: IPC6: Interrupt Priority Control Register 6

      127
    • Register 8-28: IPC7: Interrupt Priority Control Register 7

      128
    • Register 8-29: IPC8: Interrupt Priority Control Register 8

      129
    • Register 8-30: IPC9: Interrupt Priority Control Register 9

      130
    • Register 8-31: IPC10: Interrupt Priority Control Register 10

      131
    • Register 8-32: IPC11: Interrupt Priority Control Register 11

      132
    • Register 8-33: IPC12: Interrupt Priority Control Register 12

      133
    • Register 8-34: IPC13: Interrupt Priority Control Register 13

      134
    • Register 8-35: IPC15: Interrupt Priority Control Register 15

      135
    • Register 8-36: IPC16: Interrupt Priority Control Register 16

      136
    • Register 8-37: IPC18: Interrupt Priority Control Register 18

      137
    • Register 8-38: IPC19: Interrupt Priority Control Register 19

      137
    • Register 8-39: IPC20: Interrupt Priority Control Register 20

      138
    • Register 8-40: IPC21: Interrupt Priority Control Register 21

      139
    • Register 8-41: IPC22: Interrupt Priority Control Register 22

      140
    • Register 8-42: IPC25: Interrupt Priority Control Register 25

      141
    • Register 8-43: IPC29: Interrupt Priority Control Register 29

      141
    • Register 8-44: INTTREG: Interrupt Controller Test Register

      142
  • 8.4 Interrupt Setup Procedures

    143
    • 8.4.1 Initialization

      143
    • 8.4.2 Interrupt Service Routine (ISR)

      143
    • 8.4.3 Trap Service Routine (TSR)

      143
    • 8.4.4 Interrupt Disable

      143
• 9.0 Oscillator Configuration

  145
  • FIGURE 9-1: PIC24FJ128GA310 family Clock Diagram

    145
  • 9.1 CPU Clocking Scheme

    146
  • 9.2 Initial Configuration on POR

    146
    • 9.2.1 Clock Switching Mode Configuration Bits

      146
      • TABLE 9-1: Configuration Bit Values for Clock Selection

        146
  • 9.3 Control Registers

    147
    • Register 9-1: OSCCON: Oscillator Control Register

      147
    • Register 9-2: CLKDIV: Clock Divider Register

      149
    • Register 9-3: OSCTUN: FRC Oscillator Tune Register

      150
  • 9.4 Clock Switching Operation

    150
    • 9.4.1 Enabling Clock Switching

      150
    • 9.4.2 Oscillator Switching Sequence

      151
      • EXAMPLE 9-1: Basic Code Sequence for Clock Switching

        151
  • 9.5 Secondary Oscillator (SOSC)

    152
    • 9.5.1 Basic SOSC Operation

      152
    • 9.5.2 LOW-POWER SOSC OPERATION

      152
    • 9.5.3 External (Digital) Clock Mode (SCLKI)

      152
    • 9.5.4 SOSC LAYOUT Considerations

      152
  • 9.6 Reference Clock Output

    152
    • Register 9-4: REFOCON: Reference Oscillator Control Register

      153
• 10.0 Power-Saving Features

  155
  • 10.1 Overview of Power-Saving Modes

    155
    • TABLE 10-1: Operating Modes for PIC24FJ128GA310 family Devices

      155
    • TABLE 10-2: Exiting Power Saving Modes

      156
    • 10.1.1 Instruction-Based Power-Saving Modes

      156
      • EXAMPLE 10-1: PWRSAV Instruction Syntax

        156
    • 10.1.2 Hardware-Based Power-Saving Mode

      157
    • 10.1.3 Low-Voltage/Retention Regulator

      157
  • 10.2 Idle Mode

    157
  • 10.3 Sleep Mode

    157
    • 10.3.1 Low-Voltage/Retention Sleep Mode

      157
  • 10.4 Deep Sleep Mode

    158
    • 10.4.1 Entering Deep Sleep Mode

      158
      • EXAMPLE 10-2: The Repeat Sequence

        158
    • 10.4.2 Exiting Deep Sleep Modes

      159
    • 10.4.3 Saving Context Data with the DSGPRn Registers

      159
    • 10.4.4 I/O Pins in Deep Sleep Modes

      159
    • 10.4.5 Deep Sleep WDT

      160
    • 10.4.6 Checking and Clearing the Status of Deep Sleep

      160
    • 10.4.7 Power-on Resets (PORs)

      160
  • 10.5 Vbat Mode

    160
    • 10.5.1 Vbat mode with no RTCC

      161
    • 10.5.2 WAKE-UP FROM Vbat modes

      161
    • 10.5.3 I/O PINS DURING Vbat modes

      161
    • 10.5.4 Saving Context Data with the DSGPRn Registers

      161
      • Register 10-1: DSCON: Deep Sleep Control Register(1)

        162
      • Register 10-2: DSWAKE: Deep Sleep Wake-Up Source Register(1)

        163
      • Register 10-3: RCON2: Reset and System Control Register 2

        164
  • 10.6 Clock Frequency and Clock Switching

    165
  • 10.7 Doze Mode

    165
  • 10.8 Selective Peripheral Module Control

    165
• 11.0 I/O Ports

  167
  • 11.1 Parallel I/O (PIO) Ports

    167
    • FIGURE 11-1: Block Diagram of a Typical Shared Port Structure

      167
    • 11.1.1 I/O Port Write/Read Timing

      168
    • 11.1.2 Open-Drain Configuration

      168
  • 11.2 Configuring Analog Port Pins (ANSx)

    168
    • 11.2.1 Analog Input Pins and Voltage Considerations

      168
      • TABLE 11-1: Configuring Analog/Digital Function of an I/O Pin

        168
      • TABLE 11-2: Input Voltage Levels for Port or Pin Tolerated Description Input

        168
      • Register 11-1: ANSA: PortA Analog Function Selection Register

        169
      • Register 11-2: ANSB: PortB Analog Function Selection Register

        169
      • Register 11-3: ANSC: PortC Analog Function Selection Register

        170
      • Register 11-4: ANSD: PortD Analog Function Selection Register

        170
      • Register 11-5: ANSE: PortE Analog Function Selection Register(1)

        171
      • Register 11-6: ANSG: PortG Analog Function Selection Register

        171
  • 11.3 Input Change Notification

    172
    • EXAMPLE 11-1: Port Write/Read in Assembly

      172
    • EXAMPLE 11-2: Port Write/Read in ‘C’

      172
  • 11.4 Peripheral Pin Select (PPS)

    173
    • 11.4.1 Available Pins

      173
    • 11.4.2 Available Peripherals

      173
    • 11.4.3 Controlling Peripheral Pin Select

      173
      • TABLE 11-3: Selectable Input Sources (Maps Input to Function)(1)

        174
      • TABLE 11-4: Selectable Output Sources (Maps Function to Output)

        175
    • 11.4.4 Controlling Configuration Changes

      176
      • TABLE 11-5: Remappable Pin Exceptions for PIC24FJ128GA310 family Devices

        176
    • 11.4.5 Considerations for Peripheral Pin Selection

      177
      • EXAMPLE 11-3: Configuring UART1 Input and Output Functions

        177
    • 11.4.6 Peripheral Pin Select Registers

      178
      • Register 11-7: RPINR0: Peripheral Pin Select Input Register 0

        178
      • Register 11-8: RPINR1: Peripheral Pin Select Input Register 1

        178
      • Register 11-9: RPINR2: Peripheral Pin Select Input Register 2

        179
      • Register 11-10: RPINR3: Peripheral Pin Select Input Register 3

        179
      • Register 11-11: RPINR4: Peripheral Pin Select Input Register 4

        180
      • Register 11-12: RPINR7: Peripheral Pin Select Input Register 7

        180
      • Register 11-13: RPINR8: Peripheral Pin Select Input Register 8

        181
      • Register 11-14: RPINR9: Peripheral Pin Select Input Register 9

        181
      • Register 11-15: RPINR10: Peripheral Pin Select Input Register 10

        182
      • Register 11-16: RPINR11: Peripheral Pin Select Input Register 11

        182
      • Register 11-17: RPINR17: Peripheral Pin Select Input Register 17

        183
      • Register 11-18: RPINR18: Peripheral Pin Select Input Register 18

        183
      • Register 11-19: RPINR19: Peripheral Pin Select Input Register 19

        184
      • Register 11-20: RPINR20: Peripheral Pin Select Input Register 20

        184
      • Register 11-21: RPINR21: Peripheral Pin Select Input Register 21

        185
      • Register 11-22: RPINR22: Peripheral Pin Select Input Register 22

        185
      • Register 11-23: RPINR23: Peripheral Pin Select Input Register 23

        186
      • Register 11-24: RPINR27: Peripheral Pin Select Input Register 27

        186
      • Register 11-25: RPINR30: Peripheral Pin Select Input Register 30

        187
      • Register 11-26: RPINR31: Peripheral Pin Select Input Register 31

        187
      • Register 11-27: RPOR0: Peripheral Pin Select Output Register 0

        188
      • Register 11-28: RPOR1: Peripheral Pin Select Output Register 1

        188
      • Register 11-29: RPOR2: Peripheral Pin Select Output Register 2

        189
      • Register 11-30: RPOR3: Peripheral Pin Select Output Register 3

        189
      • Register 11-31: RPOR4: Peripheral Pin Select Output Register 4

        190
      • Register 11-32: RPOR5: Peripheral Pin Select Output Register 5

        190
      • Register 11-33: RPOR6: Peripheral Pin Select Output Register 6

        191
      • Register 11-34: RPOR7: Peripheral Pin Select Output Register 7

        191
      • Register 11-35: RPOR8: Peripheral Pin Select Output Register 8

        192
      • Register 11-36: RPOR9: Peripheral Pin Select Output Register 9

        192
      • Register 11-37: RPOR10: Peripheral Pin Select Output Register 10

        193
      • Register 11-38: RPOR11: Peripheral Pin Select Output Register 11

        193
      • Register 11-39: RPOR12: Peripheral Pin Select Output Register 12

        194
      • Register 11-40: RPOR13: Peripheral Pin Select Output Register 13

        194
      • Register 11-41: RPOR14: Peripheral Pin Select Output Register 14

        195
      • Register 11-42: RPOR15: Peripheral Pin Select Output Register 15

        195
• 12.0 Timer1

  197
  • FIGURE 12-1: 16-bit Timer1 Module Block Diagram

    197
  • Register 12-1: T1CON: Timer1 Control Register(1)

    198
• 13.0 Timer2/3 and Timer4/5

  199
  • FIGURE 13-1: Timer2/3 and Timer4/5 (32-bit) Block Diagram

    200
  • FIGURE 13-2: Timer2 and Timer4 (16-bit Synchronous) Block Diagram

    201
  • FIGURE 13-3: Timer3 and Timer5 (16-bit Asynchronous) Block Diagram

    201
  • Register 13-1: TxCON: Timer2 and Timer4 Control Register(3)

    202
  • Register 13-2: TyCON: Timer3 and Timer5 Control Register(3)

    203
• 14.0 Input Capture with Dedicated Timers

  205
  • 14.1 General Operating Modes

    205
    • 14.1.1 Synchronous and Trigger modes

      205
      • FIGURE 14-1: Input Capture Block Diagram

        205
    • 14.1.2 Cascaded (32-bit) Mode

      206
  • 14.2 Capture Operations

    206
    • Register 14-1: ICxCON1: Input Capture x Control Register 1

      207
    • Register 14-2: ICxCON2: Input Capture x Control Register 2

      208
• 15.0 Output Compare with Dedicated Timers

  211
  • 15.1 General Operating Modes

    211
    • 15.1.1 Synchronous and Trigger modes

      211
    • 15.1.2 Cascaded (32-bit) Mode

      211
      • FIGURE 15-1: Output Compare Block Diagram (16-bit Mode)

        212
  • 15.2 Compare Operations

    212
  • 15.3 Pulse-Width Modulation (PWM) Mode

    213
    • FIGURE 15-2: Output Compare Block Diagram (Double-Buffered, 16-bit PWM Mode)

      214
    • 15.3.1 PWM Period

      214
      • EQUATION 15-1: Calculating the PWM Period(1)

        214
    • 15.3.2 PWM Duty Cycle

      215
      • EQUATION 15-2: Calculation for Maximum PWM Resolution(1)

        215
      • EXAMPLE 15-1: PWM Period and Duty Cycle Calculations(1)

        215
      • TABLE 15-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)(1)

        215
      • TABLE 15-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)(1)

        215
      • Register 15-1: OCxCON1: Output Compare x Control Register 1

        216
      • Register 15-2: OCxCON2: Output Compare x Control Register 2

        218
• 16.0 Serial Peripheral Interface (SPI)

  221
  • FIGURE 16-1: SPIx Module Block Diagram (Standard Mode)

    222
  • FIGURE 16-2: SPIx Module Block Diagram (Enhanced Mode)

    223
  • Register 16-1: SPIxSTAT: SPIx Status and Control Register

    224
  • Register 16-2: SPIxCON1: SPIx Control Register 1

    226
  • Register 16-3: SPIxCON2: SPIx Control Register 2

    228
  • FIGURE 16-3: SPI Master/Slave Connection (Standard Mode)

    229
  • FIGURE 16-4: SPI Master/Slave Connection (Enhanced Buffer Modes)

    229
  • FIGURE 16-5: SPI Master, Frame Master Connection Diagram

    230
  • FIGURE 16-6: SPI Master, Frame Slave Connection Diagram

    230
  • FIGURE 16-7: SPI Slave, Frame Master Connection Diagram

    230
  • FIGURE 16-8: SPI Slave, Frame Slave Connection Diagram

    230
  • EQUATION 16-1: Relationship Between Device and SPI Clock Speed(1)

    231
  • TABLE 16-1: Sample SCKx Frequencies(1,2)

    231
• 17.0 Inter-Integrated Circuit™ (I2C™)

  233
  • 17.1 Communicating as a Master in a Single Master Environment

    233
    • FIGURE 17-1: I2C™ Block Diagram

      234
  • 17.2 Setting Baud Rate When Operating as a Bus Master

    235
    • EQUATION 17-1: Computing Baud Rate Reload Value(1,2)

      235
  • 17.3 Slave Address Masking

    235
    • TABLE 17-1: I2C™ Clock Rates(1,2)

      235
    • TABLE 17-2: I2C™ reserved addresses(1)

      235
    • Register 17-1: I2CxCON: I2Cx Control Register

      236
    • Register 17-2: I2CxSTAT: I2Cx Status Register

      238
    • Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      239
• 18.0 Universal Asynchronous Receiver Transmitter (UART)

  241
  • FIGURE 18-1: UART Simplified Block Diagram

    241
  • 18.1 UART Baud Rate Generator (BRG)

    242
    • EQUATION 18-1: UART Baud Rate with BRGH = 0(1,2)

      242
    • EQUATION 18-2: UART Baud Rate with BRGH = 1(1,2)

      242
    • EXAMPLE 18-1: Baud Rate Error Calculation (BRGH = 0)(1)

      242
  • 18.2 Transmitting in 8-Bit Data Mode

    243
  • 18.3 Transmitting in 9-Bit Data Mode

    243
  • 18.4 Break and Sync Transmit Sequence

    243
  • 18.5 Receiving in 8-Bit or 9-Bit Data Mode

    243
  • 18.6 Operation of UxCTS and UxRTS Control Pins

    243
  • 18.7 Infrared Support

    243
    • 18.7.1 IrDA Clock Output for External IrDA Support

      243
    • 18.7.2 Built-in IrDA Encoder and Decoder

      243
      • Register 18-1: UxMODE: UARTx Mode Register

        244
      • Register 18-2: UxSTA: UARTx Status and Control Register

        246
• 19.0 Data Signal Modulator

  249
  • FIGURE 19-1: Simplified Block Diagram of the Data SIgnal Modulator

    249
  • Register 19-1: MDCON: Modulator Control Register

    250
  • Register 19-2: MDSRC: Modulator Source Control Register

    251
  • Register 19-3: MDCAR: Modulator Carrier Control Register

    252
• 20.0 Enhanced Parallel Master Port (EPMP)

  253
  • 20.1 Specific Package Variations

    253
    • TABLE 20-1: EPMP Feature Differences By Device Pin Count

      253
    • TABLE 20-2: Enhanced Parallel Master Port Pin Descriptions

      254
    • Register 20-1: PMCON1: EPMP Control Register 1

      255
    • Register 20-2: PMCON2: EPMP Control Register 2

      256
    • Register 20-3: PMCON3: EPMP Control Register 3

      257
    • Register 20-4: PMCON4: EPMP Control Register 4

      258
    • Register 20-5: PMCSxCF: Chip Select x Configuration Register

      259
    • Register 20-6: PMCSxBS: Chip Select x Base Address Register(2)

      260
    • Register 20-7: PMCSxMD: Chip Select x Mode Register

      261
    • Register 20-8: PMSTAT: EPMP Status Register (Slave mode only)

      262
    • Register 20-9: PADCFG1: Pad Configuration Control Register

      263
• 21.0 Liquid Crystal Display (LCD) Controller

  265
  • FIGURE 21-1: LCD Controller Module Block Diagram

    265
  • 21.1 Registers

    266
    • Register 21-1: LCDCON: LCD Control Register

      266
    • Register 21-2: LCDREG: LCD Charge Pump Control Register

      268
    • Register 21-3: LCDPS: LCD Phase Register

      269
    • Register 21-4: LCDSEx: LCD SEGMENT x Enable Register

      270
    • Register 21-5: LCDDATAx: LCD DATA x Register

      270
    • TABLE 21-1: LCDDATA Registers And Bits For Segment And COM Combinations

      271
    • Register 21-6: LCDREF: LCD Reference Ladder Control Register

      272
• 22.0 Real-Time Clock and Calendar (RTCC)

  275
  • 22.1 RTCC Source Clock

    275
    • FIGURE 22-1: RTCC Block Diagram

      275
  • 22.2 RTCC Module Registers

    276
    • 22.2.1 Register Mapping

      276
      • TABLE 22-1: RTCVAL Register Mapping

        276
      • TABLE 22-2: ALRMVAL Register Mapping

        276
    • 22.2.2 Write Lock

      276
    • 22.2.3 Selecting RTCC Clock Source

      276
      • EXAMPLE 22-1: Setting the RTCWREN Bit

        276
  • 22.3 Registers

    277
    • 22.3.1 RTCC Control Registers

      277
      • Register 22-1: RCFGCAL: RTCC Calibration/Configuration Register(1)

        277
      • Register 22-2: RTCPWC: RTCC Power Control Register(1)

        279
      • Register 22-3: ALCFGRPT: Alarm Configuration Register

        280
    • 22.3.2 RTCVAL Register Mappings

      281
      • Register 22-4: YEAR: Year Value Register(1)

        281
      • Register 22-5: MTHDY: Month and Day Value Register(1)

        281
      • Register 22-6: WKDYHR: Weekday and Hours Value Register(1)

        282
      • Register 22-7: MINSEC: Minutes and Seconds Value Register

        282
    • 22.3.3 ALRMVAL Register Mappings

      283
      • Register 22-8: ALMTHDY: Alarm Month and Day Value Register(1)

        283
      • Register 22-9: ALWDHR: Alarm Weekday and Hours Value Register(1)

        283
      • Register 22-10: ALMINSEC: Alarm Minutes and Seconds Value Register

        284
      • Register 22-11: RTCCSWT: Power Control and Sample Window Timer Register(1)

        285
  • 22.4 Calibration

    286
    • EQUATION 22-1:

      286
  • 22.5 Alarm

    286
    • 22.5.1 Configuring The Alarm

      286
    • 22.5.2 Alarm Interrupt

      286
      • FIGURE 22-2: Alarm Mask Settings

        287
  • 22.6 POWER CONTROL

    287
  • 22.7 RTCC Vbat OPERATION

    287
• 23.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator

  289
  • FIGURE 23-1: CRC Block Diagram

    289
  • FIGURE 23-2: CRC Shift Engine Detail

    289
  • 23.1 User Interface

    290
    • 23.1.1 Polynomial Interface

      290
      • EQUATION 23-1: 16-Bit, 32-bit CRC Polynomials

        290
    • 23.1.2 DATA INTERFACE

      290
      • TABLE 23-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALs

        290
    • 23.1.3 Data Shift Direction

      291
    • 23.1.4 Interrupt Operation

      291
    • 23.1.5 Typical Operation

      291
      • Register 23-1: CRCCON1: CRC Control 1 Register

        292
      • Register 23-2: CRCCON2: CRC Control 2 Register

        293
      • Register 23-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE

        293
      • Register 23-4: CRCXORH: CRC XOR High Register

        294
• 24.0 12-Bit A/D Converter with Threshold Scan

  295
  • 24.1 Basic Operation

    295
    • FIGURE 24-1: 12-Bit A/D Converter Block Diagram (PIC24FJ128GA310 family)

      296
  • 24.2 Extended DMA Operations

    297
    • 24.2.1 Extended Buffer Mode

      297
    • 24.2.2 PIA Mode

      297
  • 24.3 A/D Operation with Vbat

    297
  • 24.4 Registers

    298
    • TABLE 24-1: Indirect Address Generation in PIA Mode

      298
    • FIGURE 24-2: Example of Buffer Address Generation in PIA Mode (4-Word Buffers Per Channel)

      299
    • Register 24-1: AD1CON1: A/D Control Register 1

      300
    • Register 24-2: AD1CON2: A/D Control Register 2

      302
    • Register 24-3: AD1CON3: A/D Control Register 3

      303
    • Register 24-4: AD1CON4: A/D control register 4

      304
    • Register 24-5: AD1CON5: A/D Control Register 5

      305
    • Register 24-6: AD1CHS: A/D Sample Select Register

      306
    • Register 24-7: ANCFG: A/D Band Gap rEFERENCE cONFIGURATION

      307
    • Register 24-8: AD1CHITH: A/D Scan Compare Hit Register (High Word)

      308
    • Register 24-9: AD1CHITL: A/D Scan Compare Hit Register (Low Word)

      308
    • Register 24-10: AD1CSSH: A/D Input Scan Select Register (High Word)

      309
    • Register 24-11: AD1CSSL: A/D Input Scan Select Register (Low word)

      309
    • Register 24-12: AD1CTMENH: CTMU Enable Register (High Word)(1)

      310
    • Register 24-13: AD1CTMENL: CTMU Enable Register (Low Word)(1)

      310
    • FIGURE 24-3: 10-Bit A/D Converter Analog Input Model

      311
    • EQUATION 24-1: A/D Conversion Clock Period

      311
    • FIGURE 24-4: 12-bit A/D Transfer Function

      312
    • FIGURE 24-5: 10-bit A/D Transfer Function

      313
• 25.0 Triple Comparator Module

  315
  • FIGURE 25-1: Triple Comparator Module Block Diagram

    315
  • FIGURE 25-2: Individual Comparator Configurations when CREF = 0

    316
  • FIGURE 25-3: Individual Comparator Configurations when CREF = 1 and CVREFP = 0

    317
  • FIGURE 25-4: Individual Comparator Configurations when CREF = 1 and CVREFP = 1

    317
  • Register 25-1: CMxCON: Comparator x Control Registers (Comparators 1 Through 3)

    318
  • Register 25-2: CMSTAT: Comparator Module Status Register

    319
• 26.0 Comparator Voltage Reference

  321
  • 26.1 Configuring the Comparator Voltage Reference

    321
    • FIGURE 26-1: Comparator Voltage Reference Block Diagram

      321
    • Register 26-1: CVRCON: Comparator Voltage Reference Control Register

      322
• 27.0 Charge Time Measurement Unit (CTMU)

  323
  • 27.1 Measuring Capacitance

    323
    • EQUATION 27-1:

      323
    • FIGURE 27-1: Typical Connections and Internal Configuration for Capacitance Measurement

      324
  • 27.2 Measuring Time

    324
  • 27.3 Pulse Generation and Delay

    324
    • FIGURE 27-2: Typical Connections and Internal Configuration for Time Measurement

      325
    • FIGURE 27-3: Typical Connections and Internal Configuration for Pulse Delay Generation

      325
    • Register 27-1: CTMUCON1: CTMU Control Register 1

      326
    • Register 27-2: CTMUCON2: CTMU ControL Register 2

      327
    • Register 27-3: CTMUICON: CTMU current Control Register

      329
• 28.0 High/Low-Voltage Detect (HLVD)

  331
  • FIGURE 28-1: High/Low-Voltage Detect (HLVD) Module Block Diagram

    331
  • Register 28-1: HLVDCON: High/Low-Voltage Detect Control Register

    332
• 29.0 Special Features

  333
  • 29.1 Configuration Bits

    333
    • 29.1.1 Considerations for Configuring PIC24FJ128GA310 family Devices

      333
      • TABLE 29-1: Flash Configuration Word Locations for PIC24FJ128GA310 family Devices

        333
      • Register 29-1: CW1: Flash Configuration Word 1

        334
      • Register 29-2: CW2: Flash Configuration Word 2

        336
      • Register 29-3: CW3: Flash Configuration Word 3

        338
      • Register 29-4: CW4: Flash Configuration Word 4

        340
      • Register 29-5: DEVID: Device ID Register

        342
      • Register 29-6: DEVREV: Device Revision Register

        342
  • 29.2 On-Chip Voltage Regulator

    343
    • FIGURE 29-1: Connections for the On-Chip Regulator

      343
    • 29.2.1 On-Chip Regulator and POR

      343
    • 29.2.2 Voltage Regulator Standby Mode

      343
    • 29.2.3 Low-Voltage/Retention Regulator

      343
  • 29.3 Watchdog Timer (WDT)

    344
    • 29.3.1 Windowed Operation

      344
    • 29.3.2 Control Register

      344
      • FIGURE 29-2: WDT Block Diagram

        344
  • 29.4 Program Verification and Code Protection

    345
    • 29.4.1 General Segment Protection

      345
    • 29.4.2 Code Segment Protection

      345
      • TABLE 29-2: Code Segment Protection Configuration Options

        345
    • 29.4.3 Configuration Register Protection

      346
  • 29.5 JTAG Interface

    346
  • 29.6 In-Circuit Serial Programming

    346
  • 29.7 In-Circuit Debugger

    346
• 30.0 Development Support

  347
• 31.0 Instruction Set Summary

  351
  • TABLE 31-1: Symbols Used in Opcode Descriptions

    352
  • TABLE 31-2: Instruction Set Overview

    353
• 32.0 Electrical Characteristics

  359
  • Absolute Maximum Ratings(†)

    359
  • 32.1 DC Characteristics

    360
    • FIGURE 32-1: PIC24FJ128GA310 family Voltage-Frequency Graph (Industrial)

      360
    • TABLE 32-1: Thermal Operating Conditions

      360
    • TABLE 32-2: Thermal Packaging Characteristics

      360
    • TABLE 32-3: DC Characteristics: Temperature and Voltage Specifications

      361
    • TABLE 32-4: DC Characteristics: Operating Current (Idd)

      361
    • TABLE 32-5: DC Characteristics: Idle Current (Iidle)

      362
    • TABLE 32-6: DC Characteristics: Power-Down Current (Ipd)

      363
    • TABLE 32-7: DC Characteristics: DCurrent (BOR, WDT, DSBOR, DSWDT, LCD)

      364
    • TABLE 32-8: DC Characteristics: I/O Pin Input Specifications

      365
    • TABLE 32-9: DC Characteristics: I/O Pin Output Specifications

      366
    • TABLE 32-10: DC Characteristics: Program Memory

      366
    • TABLE 32-11: Internal Voltage Regulator Specifications

      367
    • TABLE 32-12: Vbat Operating Voltage Specifications

      367
    • TABLE 32-13: CTMU Current Source Specifications

      367
    • TABLE 32-14: High/Low-Voltage Detect Characteristics

      368
    • TABLE 32-15: Comparator DC Specifications

      368
    • TABLE 32-16: Comparator Voltage Reference DC Specifications

      368
  • 32.2 AC Characteristics and Timing Parameters

    369
    • TABLE 32-17: Temperature and Voltage Specifications – AC

      369
    • FIGURE 32-2: Load Conditions for Device Timing Specifications

      369
    • TABLE 32-18: Capacitive Loading Requirements on Output Pins

      369
    • FIGURE 32-3: External Clock Timing

      370
    • TABLE 32-19: External Clock Timing Requirements

      370
    • TABLE 32-20: PLL Clock Timing Specifications (Vdd = 2.2V to 3.6V)

      371
    • TABLE 32-21: Internal RC Accuracy

      371
    • TABLE 32-22: RC Oscillator Start-Up Time

      371
    • FIGURE 32-4: CLKO and I/O Timing Characteristics

      372
    • TABLE 32-23: CLKO and I/O Timing Requirements

      372
    • TABLE 32-24: Reset and Brown-out Reset Requirements

      373
    • TABLE 32-25: A/D Module Specifications

      374
    • TABLE 32-26: A/D Conversion Timing Requirements(1)

      375
• 33.0 Packaging Information

  377
  • 33.1 Package Marking Information

    377
  • 33.2 Package Marking Information

    378
  • 33.3 Package Details

    379
• Appendix A: Revision History

  393
  • Revision A (March 2010)

    393
  • Revision B (May 2011)

    393
  • Revision C (July 2011)

    393
  • Revision D (August 2011)

    393
  • Revision E (October 2011)

    393
  • Revision F (November 2011)

    393
• INDEX

  395
• The Microchip Web Site

  401
• Customer Change Notification Service

  401
• Customer Support

  401
• Reader Response

  402
• Product Identification System

  403
• Worldwide Sales and Service

  406