Microchip Technology MA240029 データシート
PIC24FJ128GA310 FAMILY
DS39996F-page 178
2010-2011 Microchip Technology Inc.
11.4.6
PERIPHERAL PIN SELECT
REGISTERS
REGISTERS
The PIC24FJ128GA310 family of devices implements
a total of 35 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (19)
• Output Remappable Peripheral Registers (16)
a total of 35 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (19)
• Output Remappable Peripheral Registers (16)
Note:
Input and output register values can only
be changed if IOLOCK (OSCCON<6>) = 0.
See
be changed if IOLOCK (OSCCON<6>) = 0.
See
for a specific command sequence.
REGISTER 11-7:
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented:
Read as ‘0’
bit 13-8
INT1R<5:0>:
Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits
bit 7-0
Unimplemented:
Read as ‘0’
REGISTER 11-8:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT3R5
INT3R4
INT3R3
INT3R2
INT3R1
INT3R0
bit 15
bit 8
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented:
Read as ‘0’
bit 13-8
INT3R<5:0>:
Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits
bit 7-6
Unimplemented:
Read as ‘0’
bit 5-0
INT2R<5:0>:
Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits