Microchip Technology MA240029 データシート
PIC24FJ128GA310 FAMILY
DS39996F-page 266
2010-2011 Microchip Technology Inc.
21.1
Registers
The LCD controller has up to 40 registers:
• LCD Control Register (LCDCON)
• LCD Charge Pump Control Register (LCDREG)
• LCD Phase Register (LCDPS)
• LCD Voltage Ladder Control Register (LCDREF)
• Four LCD Segment Enable Registers
• LCD Control Register (LCDCON)
• LCD Charge Pump Control Register (LCDREG)
• LCD Phase Register (LCDPS)
• LCD Voltage Ladder Control Register (LCDREF)
• Four LCD Segment Enable Registers
(LCDSE3:LCDSE0)
• Up to 32 LCD Data Registers
(LCDDATA31:LCDDATA0)
REGISTER 21-1:
LCDCON: LCD CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
LCDEN
—
LCDSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/C-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SLPEN
WERR
CS1
CS0
LMUX2
LMUX1
LMUX0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
LCDEN
: LCD Driver Enable bit
1
= LCD driver module is enabled
0
= LCD driver module is disabled
bit 14
Unimplemented:
Read as ‘0’
bit 13
LCDSIDL
: Stop LCD Drive in CPU Idle Mode Control bit
1
= LCD driver Halts in CPU Idle mode
0
= LCD driver continues to operate in CPU Idle mode
bit 12-7
Unimplemented:
Read as ‘0’
bit 6
SLPEN
: LCD Driver Enable in Sleep mode bit
1
= LCD driver module is disabled in Sleep mode
0
= LCD driver module is enabled in Sleep mode
bit 5
WERR
: LCD Write Failed Error bit
1
= LCDDATAx register is written while WA (LCDPS<4>) = 0 (must be cleared in software)
0
= No LCD write error
bit 4-3
CS<1:0>
: Clock Source Select bits
00
= FRC
01
= LPRC
1x
= SOSC