Microchip Technology MA240029 データシート
2010-2011 Microchip Technology Inc.
DS39996F-page 307
PIC24FJ128GA310 FAMILY
bit 7-5
CH0NA<2:0>:
Sample A Channel 0 Negative Input Select bits
Same definitions as for CHONB<2:0>.
bit 4-0
CH0SA<4:0>:
Sample A Channel 0 Positive Input Select bits
Same definitions as for CHOSB<4:0>.
REGISTER 24-6:
AD1CHS: A/D SAMPLE SELECT REGISTER (CONTINUED)
Note 1:
These input channels do not have corresponding memory mapped result buffers.
2:
These channels are implemented in 100-pin devices only.
REGISTER 24-7:
ANCFG: A/D BAND GAP REFERENCE CONFIGURATION
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
VBG6EN
VBG2EN
VBGEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
Unimplemented:
Read as ‘0’
bit 2
VBG6EN:
A/D Input V
BG
/6 Enable bit
1
= Band gap voltage, divided by six reference (V
BG
/6), is enabled
0
= Band gap, divided by six reference (V
BG
/6), is disabled
bit 1
VBG2EN:
A/D Input V
BG
/6 Enable bit
1
= Band gap voltage, divided by two reference (V
BG
/6), is enabled
0
= Band gap, divided by two reference (V
BG
/6), is disabled
bit 0
VBGEN:
A/D Input V
BG
/6 Enable bit
1
= Band gap voltage reference (V
BG
/6) is enabled
0
= Band gap reference (V
BG
/6) is disabled