Microchip Technology MA240029 データシート
2010-2011 Microchip Technology Inc.
DS39996F-page 39
PIC24FJ128GA310 FAMILY
REGISTER 3-2:
CORCON: CPU CORE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
R-1
U-0
U-0
—
—
—
—
IPL3
(
)
r
—
—
bit 7
bit 0
Legend:
C = Clearable bit
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
Unimplemented:
Read as ‘0’
bit 3
IPL3:
CPU Interrupt Priority Level Status bit
1
= CPU interrupt priority level is greater than 7
0
= CPU interrupt priority level is 7 or less
bit 2
Reserved:
Read as ‘1’
bit 1-0
Unimplemented:
Read as ‘0’
Note 1:
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level; see
for bit description.