Microchip Technology MA240029 データシート
2010-2011 Microchip Technology Inc.
DS39996F-page 43
PIC24FJ128GA310 FAMILY
4.2
Data Memory Space
The PIC24F core has a 16-bit wide data memory space,
addressable as a single linear range. The data space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The data space
memory map is shown in
addressable as a single linear range. The data space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The data space
memory map is shown in
The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This
gives a DS address range of 64 Kbytes or 32K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
space point to bytes within the Data Space (DS). This
gives a DS address range of 64 Kbytes or 32K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
.
The lower half of DS is compatible with previous PIC24F
microcontrollers without EDS. All PIC24FJ128GA310
family devices implement 8 Kbytes of data RAM in the
lower half of DS, from 0800h to 27FFh.
microcontrollers without EDS. All PIC24FJ128GA310
family devices implement 8 Kbytes of data RAM in the
lower half of DS, from 0800h to 27FFh.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
byte-addressable, 16-bit wide blocks. Data is aligned
in data memory and registers as 16-bit words, but all
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
FIGURE 4-3:
DATA SPACE MEMORY MAP FOR PIC24FJ128GA310 FAMILY DEVICES
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 45. “Data Memory with
Extended Data Space (EDS)
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F Family Reference Manual”,
Section 45. “Data Memory with
Extended Data Space (EDS)
” (DS39733).
The information in this data sheet
supersedes the information in the FRM.
supersedes the information in the FRM.
Note:
Memory areas not shown to scale.
0000h
07FEh
07FEh
FFFEh
LSB
Address
LSB
MSB
MSB
Address
0001h
07FFh
07FFh
1FFFh
FFFFh
8001h
8000h
7FFFh
0801h
0800h
2001h
Near
1FFEh
SFR
2000h
7FFEh
EDS Window
Space
Data Space
Upper 32 Kbytes
Data Space
2800h
2801h
(1)
Lower 32 Kbytes
Data Space
8 Kbytes Data RAM
SFR Space
Unimplemented
EDS Page 0x1
(32 Kbytes)
EDS Page 0x2
(32 Kbytes)
EDS Page 0x3 (2 Kbytes)
EDS Page 0x4
EDS Page 0x1FF
EDS Page 0x200
EDS Page 0x2FF
EDS Page 0x300
EDS Page 0x3FF
Internal Extended
Data RAM (66 Kbytes)
Data RAM (66 Kbytes)
EPMP Memory Space
Program Space Visibility
Area to Access Lower
Word of Program Memory
Area to Access Lower
Word of Program Memory
Program Space Visibility
Area to Access Upper
Word of Program Memory
Area to Access Upper
Word of Program Memory