Microchip Technology MA240029 データシート
PIC24FJ128GA310 FAMILY
DS39996F-page 76
2010-2011 Microchip Technology Inc.
5.1
Summary of DMA Operations
The DMA Controller is capable of moving data between
addresses according to a number of different parame-
ters. Each of these parameters can be independently
configured for any transaction; in addition, any or all of
the DMA channels can independently perform a differ-
ent transaction at the same time. Transactions are
classified by these parameters:
• Source and destination (SFRs and data RAM)
• Data Size (byte or word)
• Trigger source
• Transfer mode (One-Shot, Repeated or
addresses according to a number of different parame-
ters. Each of these parameters can be independently
configured for any transaction; in addition, any or all of
the DMA channels can independently perform a differ-
ent transaction at the same time. Transactions are
classified by these parameters:
• Source and destination (SFRs and data RAM)
• Data Size (byte or word)
• Trigger source
• Transfer mode (One-Shot, Repeated or
Continuous)
• Addressing modes (fixed address or address
blocks, with or without address increment/
decrement)
decrement)
In addition, the DMA controller provides channel priority
arbitration for all channels.
arbitration for all channels.
5.1.1
SOURCE AND DESTINATION
Using the DMA Controller, data may be moved
between any two addresses in the data space. The
SFR space (0000h to 07FFh) or the data RAM space
(0800h to FFFFh) can serve as either the source or the
destination. Data can be moved between these areas
in either direction, or between addresses in either area.
The four different combinations are shown in
between any two addresses in the data space. The
SFR space (0000h to 07FFh) or the data RAM space
(0800h to FFFFh) can serve as either the source or the
destination. Data can be moved between these areas
in either direction, or between addresses in either area.
The four different combinations are shown in
.
If it is necessary to protect areas of data RAM, the DMA
Controller allows the user to set upper and lower address
boundaries for operations in the data space above the
SFR space. The boundaries are set by the DMAH and
DMAL Limit registers. If a DMA channel attempts an
operation outside of the address boundaries, the
transaction is terminated and an interrupt is generated.
Controller allows the user to set upper and lower address
boundaries for operations in the data space above the
SFR space. The boundaries are set by the DMAH and
DMAL Limit registers. If a DMA channel attempts an
operation outside of the address boundaries, the
transaction is terminated and an interrupt is generated.
5.1.2
DATA SIZE
The DMA Controller can handle both 8-bit and 16-bit
transactions. Size is user-selectable using the SIZE bit
(DMACHn<1>). By default, each channel is configured
for word-size transactions. When byte-size transac-
tions are chosen, the LSb of the source and/or
destination address determines if the data represents
the upper or lower byte of the data RAM location.
transactions. Size is user-selectable using the SIZE bit
(DMACHn<1>). By default, each channel is configured
for word-size transactions. When byte-size transac-
tions are chosen, the LSb of the source and/or
destination address determines if the data represents
the upper or lower byte of the data RAM location.
5.1.3
TRIGGER SOURCE
The DMA Controller can use any one of the device’s
60 interrupt sources to initiate a transaction. The DMA
trigger sources are listed in reverse order their natural
interrupt priority, and are shown in
60 interrupt sources to initiate a transaction. The DMA
trigger sources are listed in reverse order their natural
interrupt priority, and are shown in
.
Since the source and destination addresses for any
transaction can be programmed independently of the
trigger source, the DMA Controller can use any trigger
to perform an operation on any peripheral. This also
allows DMA channels to be cascaded to perform more
complex transfer operations.
transaction can be programmed independently of the
trigger source, the DMA Controller can use any trigger
to perform an operation on any peripheral. This also
allows DMA channels to be cascaded to perform more
complex transfer operations.
5.1.4
TRANSFER MODE
The DMA Controller supports four types of data trans-
fers, based on the volume of data to be moved for each
trigger.
• One-Shot: A single transaction occurs for each
fers, based on the volume of data to be moved for each
trigger.
• One-Shot: A single transaction occurs for each
trigger.
• Continuous: A series of back-to-back transactions
occur for each trigger; the number of transactions
is determined by the DMACNT transaction
counter.
is determined by the DMACNT transaction
counter.
• Repeated One-Shot: A single transaction is per-
formed repeatedly, once per trigger, until the DMA
channel is disabled.
channel is disabled.
• Repeated Continuous: A series of transactions
are performed repeatedly, one cycle per trigger,
until the DMA channel is disabled.
until the DMA channel is disabled.
All transfer modes allow the option to have the source
and destination addresses and counter value automat-
ically reloaded after the completion of a transaction.
Repeated mode transfers do this automatically.
and destination addresses and counter value automat-
ically reloaded after the completion of a transaction.
Repeated mode transfers do this automatically.
5.1.5
ADDRESSING MODES
The DMA Controller also supports transfers between
single addresses or address ranges. The four basic
options are:
• Fixed-to-Fixed: Between two constant addresses
• Fixed-to-Block: From a constant source address
single addresses or address ranges. The four basic
options are:
• Fixed-to-Fixed: Between two constant addresses
• Fixed-to-Block: From a constant source address
to a range of destination addresses
• Block-to-Fixed: From a range of source
addresses to a single, constant destination
address
address
• Block-to-Block: From a range to source
addresses to a range of destination addresses
The option to select auto-increment or auto-decrement
of source and/or destination addresses is available for
Block Addressing modes.
In addition to the four basic modes, the DMA Controller
also supports Peripheral Indirect Addressing (PIA)
mode, where the source or destination address is gen-
erated jointly by the DMA controller and a PIA capable
peripheral. When enabled, the DMA channel provides
a base source and/or destination address, while the
peripheral provides a fixed-range offset address.
For PIC24FJ128GA310 family devices, the 12-bit A/D
Converter module is the only PIA-capable peripheral.
Details for its use in PIA mode are provided in
of source and/or destination addresses is available for
Block Addressing modes.
In addition to the four basic modes, the DMA Controller
also supports Peripheral Indirect Addressing (PIA)
mode, where the source or destination address is gen-
erated jointly by the DMA controller and a PIA capable
peripheral. When enabled, the DMA channel provides
a base source and/or destination address, while the
peripheral provides a fixed-range offset address.
For PIC24FJ128GA310 family devices, the 12-bit A/D
Converter module is the only PIA-capable peripheral.
Details for its use in PIA mode are provided in