Microchip Technology MA240029 データシート
PIC24FJ128GA310 FAMILY
DS39996F-page 94
2010-2011 Microchip Technology Inc.
TABLE 7-3:
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
7.4.1
POR AND LONG OSCILLATOR
START-UP TIMES
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
7.4.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
Reset Type
Clock Source
SYSRST Delay
System Clock
Delay
Notes
POR
EC
T
POR
+ T
STARTUP
+ T
RST
—
ECPLL
T
POR
+ T
STARTUP
+ T
RST
T
LOCK
XT, HS, SOSC
T
POR
+ T
STARTUP
+ T
RST
T
OST
XTPLL, HSPLL
T
POR
+ T
STARTUP
+ T
RST
T
OST
+ T
LOCK
FRC, FRCDIV
T
POR
+ T
STARTUP
+ T
RST
T
FRC
FRCPLL
T
POR
+ T
STARTUP
+ T
RST
T
FRC
+ T
LOCK
LPRC
T
POR
+ T
STARTUP
+ T
RST
T
LPRC
BOR
EC
T
STARTUP
+ T
RST
—
ECPLL
T
STARTUP
+ T
RST
T
LOCK
XT, HS, SOSC
T
STARTUP
+ T
RST
T
OST
XTPLL, HSPLL
T
STARTUP
+ T
RST
T
OST
+ T
LOCK
FRC, FRCDIV
T
STARTUP
+ T
RST
T
FRC
FRCPLL
T
STARTUP
+ T
RST
T
FRC
+ T
LOCK
LPRC
T
STARTUP
+ T
RST
T
LPRC
MCLR
Any Clock
T
RST
—
WDT
Any Clock
T
RST
—
Software
Any clock
T
RST
—
Illegal Opcode
Any Clock
T
RST
—
Uninitialized W
Any Clock
T
RST
—
Trap Conflict
Any Clock
T
RST
—
Note 1:
T
POR
= Power-on Reset delay (10
s nominal).
2:
T
STARTUP
= T
VREG
(10
s nominal when VREGS = 1 and when VREGS = 0; depends upon
WDTWIN<1:0> bits setting).
3:
T
RST
= Internal State Reset time (2
s nominal).
4:
T
OST
= Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing
the oscillator clock to the system.
5:
T
LOCK
= PLL lock time.
6:
T
FRC
and T
LPRC
= RC oscillator start-up times.
7:
If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just T
so the system clock delay is just T
FRC
, and in such cases, FRC start-up time is valid. It switches to the
primary oscillator after its respective clock delay.
8:
T
OST
= Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.