Microchip Technology MA240029 データシート
2010-2011 Microchip Technology Inc.
DS39996F-page 99
PIC24FJ128GA310 FAMILY
The CORCON register contains the IPL3 bit, which
together with the IPL<2:0> bits, indicate the current
CPU priority level. IPL3 is a read-only bit so that trap
events cannot be masked by the user software.
The interrupt controller has the Interrupt Controller Test
register, INTTREG, which displays the status of the
interrupt controller. When an interrupt request occurs,
it’s associated vector number and the new interrupt
together with the IPL<2:0> bits, indicate the current
CPU priority level. IPL3 is a read-only bit so that trap
events cannot be masked by the user software.
The interrupt controller has the Interrupt Controller Test
register, INTTREG, which displays the status of the
interrupt controller. When an interrupt request occurs,
it’s associated vector number and the new interrupt
priority level are latched into INTTREG. This informa-
tion can be used to determine a specific interrupt
source if a generic ISR is used for multiple vectors
(such as when ISR remapping is used in bootloader
applications) or to check if another interrupt is pending
while in an ISR.
All interrupt registers are described in
tion can be used to determine a specific interrupt
source if a generic ISR is used for multiple vectors
(such as when ISR remapping is used in bootloader
applications) or to check if another interrupt is pending
while in an ISR.
All interrupt registers are described in
through
in the succeeding pages.
REGISTER 8-1:
SR: ALU STATUS REGISTER (IN CPU)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0
—
—
—
—
—
—
—
DC
(
)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL2
(
IPL1
)
IPL0
(
,
RA
N
OV
(
)
Z
(
)
C
(
)
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented:
Read as ‘0’
bit 7-5
IPL<2:0>:
CPU Interrupt Priority Level Status bits
(
,
111
= CPU interrupt priority level is 7 (15); user interrupts are disabled
110
= CPU interrupt priority level is 6 (14)
101
= CPU interrupt priority level is 5 (13)
100
= CPU interrupt priority level is 4 (12)
011
= CPU interrupt priority level is 3 (11)
010
= CPU interrupt priority level is 2 (10)
001
= CPU interrupt priority level is 1 (9)
000
= CPU interrupt priority level is 0 (8)
Note 1:
See
for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to
interrupt control functions.
2:
The IPL bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU interrupt priority level.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
The value in parentheses indicates the interrupt priority level if IPL3 = 1.
3:
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.