AMD Phenom 8450 Triple-Core HD8450WCGHBOX ユーザーズマニュアル
製品コード
HD8450WCGHBOX
Product Errata
21
Revision Guide for AMD Family 10h Processors
41322
Rev. 3.16
February 2008
178 Default RdPtrInit Value Does Not Provide Sufficient Timing
Margin
Description
Insufficient separation of the read pointer and write pointer in the synchronization FIFO can lead to
setup violations in the transmit FIFO.
setup violations in the transmit FIFO.
Potential Effect on System
The setup violations may lead to data corruption.
Suggested Workaround
BIOS should program F2x[1, 0]78[3:0] (RdPtrInit) to 4’h5
.
Fix Planned
Yes