AMD Phenom 8450 Triple-Core マニュアル

目次

• Revision History

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• Processor Identification

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  • Table 1. CPUID Values for AMD Family 10h Processor Revisions

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  • Table 2. Supported Mixed Silicon Revision Configurations

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  • Table 3. String Table Reference Per Package Type

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  • Table 4. String1 Values for Socket Fr2 (1207) Processors

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  • Table 5. String2 Values for Socket Fr2 (1207) Processors

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  • Table 6. String1 Values for Socket AM2r2 Processors

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  • Table 7. String2 Values for Socket AM2r2 Processors

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• F4x164 Fixed Errata Register

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• MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length)

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  • Table 8. OSVW_ID_Length Per Processor Revision

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• MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status)

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• Product Errata

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  • Table 9. Cross-Reference of Product Revision to Errata

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  • Table 10. Cross-Reference of Errata to Processor Segments

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  • Table 11. Cross-Reference of Errata to Package Type

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  • 57 Some Data Cache Tag Eviction Errors Are Reported As Snoop Errors

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  • 60 Single Machine Check Error May Report Overflow

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  • 77 Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor is Beyond GDT/LDT Limit

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  • 178 Default RdPtrInit Value Does Not Provide Sufficient Timing Margin

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  • 244 A DIV Instruction Followed Closely By Other Divide Instructions May Yield Incorrect Results

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  • 246 Breakpoint Due to An Instruction That Has an Interrupt Shadow May Be Delivered to the Hypervisor

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  • 248 INVLPGA of A Guest Page May Not Invalidate Splintered Pages

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  • 254 Internal Resource Livelock Involving Cached TLB Reload

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  • 260 REP MOVS Instruction May Corrupt Source Address

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  • 261 Processor May Stall Entering Stop-Grant Due to Pending Data Cache Scrub

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  • 263 Incompatibility With Some DIMMs Due to DQS Duty Cycle Distortion

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  • 264 Incorrect DRAM Data Masks Asserted When DRAM Controller Data Interleaving Is Enabled

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  • 269 ITT Specification Exceeded During Power-Up Sequencing

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  • 273 Lane Select Function Is Not Available for Link BIST on 8-Bit HyperTransport™ Links In Ganged Mode

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  • 274 IDDIO Specification Exceeded During Power-Up Sequencing

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  • 278 Incorrect Memory Controller Operation In Ganged Mode

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  • 279 HyperTransport™ Link RTT and RON Specification Violations

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  • 280 Time Stamp Counter May Yield An Incorrect Value

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  • 293 Memory Instability After PWROK Assertion

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  • 295 DRAM Phy Configuration Access Failures

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  • 297 Single Machine Check Error May Report Overflow

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  • 298 L2 Eviction May Occur During Processor Operation To Set Accessed or Dirty Bit

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  • 300 Hardware Memory Clear Is Not Supported After Software DRAM Initialization

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  • 301 Performance Counters Do Not Accurately Count MFENCE or SFENCE Instructions

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  • 302 MWAIT Power Savings May Not Be Realized when Two or More Cores Monitor the Same Address

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  • 308 Processor Stall in C1 Low Power State

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  • 309 Processor Core May Execute Incorrect Instructions on Concurrent L2 and Northbridge Response

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  • 312 CVTSD2SS and CVTPD2PS Instructions May Not Round to Zero

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  • 315 FST and FSTP Instructions May Calculate Operand Address in Incorrect Mode

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  • 319 Inaccurate Temperature Measurement

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• Documentation Support

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