Analog Devices AD9737 Evaluation Board AD9737A-EBZ AD9737A-EBZ データシート
製品コード
AD9737A-EBZ
11-/14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converters
Data Sheet
AD9737A
/
AD9739A
Rev.
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
Tel: 781.329.4700
Fax: 781.461.3113
©2011-2012 Analog Devices, Inc. All rights reserved.
FEATURES
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix-mode
1.25 GHz to 3.0 GHz in mix-mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Source synchronous DDR clocking
Pin compatible with the AD9739
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
Instrumentation, automatic test equipment
Radar, avionics
FUNCTIONAL BLOCK DIAGRAM
L
V
DS
DDR
R
EC
EI
VER
DCI
SDO
SDIO
SCLK
CS
DACCLK
DCO
DB0[
13:
0]
DB1[
13:
0]
CLK DISTRIBUTION
(DIV-BY-4)
DAT
A
C
ON
TR
OLLE
R
4
-T
O
-1
DAT
A AS
S
E
M
BL
E
R
SPI
RESET
DLL
(MU CONTROLLER)
L
V
DS
DDR
R
EC
EI
VER
DAT
A
L
AT
CH
IOUTN
IOUTP
VREF
I120
IRQ
1.2V
DAC BIAS
AD9737A/AD9739A
TxDAC
CORE
09616-
001
Figure 1.
GENERAL DESCRIPTION
are 11-bit and 14-bit, 2.5 GSPS high
and functionally compatible with the
with the
exception that the
synchronization or RZ mode, and are specified to operate
between 1.6 GSPS and 2.5 GSPS.
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the
between power-up cycles, thus
allowing for possible system calibration. AC linearity and noise
performance remain the same between the
performance remain the same between the
and the
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
registers.
The
CMOS process and operate from 1.8 V and 3.3 V supplies.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix-
mode operation.
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
C