Analog Devices AD9737 Evaluation Board AD9737A-EBZ マニュアル

目次

• Features

  1
• Applications

  1
• Functional Block Diagram

  1
• General Description

  1
• Product Highlights

  1
• Revision History

  3
• Specifications

  4
  • DC Specifications

    4
  • LVDS Digital Specifications

    5
  • Serial Port Specifications

    6
  • AC Specifications

    7
• Absolute Maximum Ratings

  8
  • Thermal Resistance

    8
  • ESD Caution

    8
• Pin Configurations and Function Descriptions

  9
• Typical Performance Characteristics—AD9737A

  14
  • Static Linearity

    14
  • AC (Normal Mode)

    15
  • AC (Mix-Mode)

    17
  • One-Carrier DOCSIS Performance (Normal Mode)

    20
  • Four-Carrier DOCSIS Performance (Normal Mode)

    21
  • Eight-Carrier DOCSIS Performance (Normal Mode)

    22
  • 16-Carrier DOCSIS Performance (Normal Mode)

    23
  • 32-Carrier DOCSIS Performance (Normal Mode)

    24
  • 64- and 128-Carrier DOCSIS Performance (Normal Mode)

    25
• Typical Performance Characteristics—AD9739A

  26
  • Static Linearity

    26
  • AC (Normal Mode)

    28
  • AC (Mix-Mode)

    31
  • One-Carrier DOCSIS Performance (Normal Mode)

    33
  • Four-Carrier DOCSIS Performance (Normal Mode)

    34
  • Eight-Carrier DOCSIS Performance (Normal Mode)

    35
  • 16-Carrier DOCSIS Performance (Normal Mode)

    36
  • 32-Carrier DOCSIS Performance (Normal Mode)

    37
  • 64- and 128-Carrier DOCSIS Performance (Normal Mode)

    38
• Terminology

  39
• Serial Port Interface (SPI) Register

  40
  • SPI Register Map Description

    40
    • Reset

      40
  • SPI Operation

    40
    • Instruction Header Information

      40
• SPI Register Map

  42
  • SPI Port Configuration and Software Reset

    43
  • Power-Down LVDS Interface and TxDAC®

    43
  • Controller Clock Disable

    43
  • Interrupt Request (IRQ) Enable/Status

    44
  • TxDAC Full-Scale Current Setting (IOUTFS) and Sleep

    44
  • TxDAC Quad-Switch Mode of Operation

    44
  • DCI Phase Alignment Status

    44
  • Data Receiver Controller Configuration

    44
  • Data Receiver Controller_Data Sample Delay Value

    45
  • Data Receiver Controller_DCI Delay Value/Window and Phase Rotation

    45
  • Data Receiver Controller_Delay Line Status

    45
  • Data Receiver Controller Lock/Tracking Status

    45
  • CLK Input Common Mode

    46
  • Mu Controller Configuration and Status

    46
  • Part ID

    47
• Theory of Operation

  48
  • LVDS Data Port Interface

    49
    • Data Receiver Controller Initialization Description

      50
    • LVDS Driver and Receiver Input

      51
  • Mu Controller

    52
    • Mu Controller Initialization Description

      53
  • Interrupt Requests

    54
• Analog Interface Considerations

  55
  • Analog Modes of Operation

    55
  • Clock Input Considerations

    56
  • Voltage Reference

    57
  • Analog Outputs

    57
    • Equivalent DAC Output and Transfer Function

      57
    • Peak DAC Output Power Capability

      58
  • Output Stage Configuration

    59
  • Nonideal Spectral Artifacts

    60
  • Lab Evaluation of the AD9737A/AD9739A

    61
  • Recommended Start-Up Sequence

    61
• Outline Dimensions

  63
  • Ordering Guide

    63