Analog Devices AD1836A Evaluation Board AD1836AZ-DBRD AD1836AZ-DBRD データシート
製品コード
AD1836AZ-DBRD
Data Sheet
AD1836A
Rev. A | Page 7 of 24
Table 7. Timing Specifications (Continued)
Parameter
Comments
Min
Max Unit
AUXILIARY INTERFACE
(Master Mode)
(Master Mode)
t
XBD
AUXBCLK Delay
From MCLK Transition, 256 × f
S
Mode
From MCLK Rising, 512 × f
S
Mode
15
ns
t
XLS
AUXLRCLK Skew
From AUXBCLK Falling
–3
+3
ns
AUXILIARY INTERFACE
(Slave Mode)
(Slave Mode)
t
XBH
AUXBCLK High
60
ns
t
XBL
AUXBCLK Low
60
ns
f
XB
AUXBCLK Frequency
64 × f
S
ns
t
DLS
AUXLRCLK Setup
To AUXBCLK Rising
5
ns
t
DLH
AUXLRCLK Hold
From AUXBCLK Rising
15
ns