Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The DMA will always use SINGLE, or INCR type AHB accesses for buffer management operations. When
performing data transfers, the AHB burst length used can be programmed using bits [4:0] of the DMA
Configuration Register so that either SINGLE, INCR or fixed length incrementing bursts (INCR4, INCR8 or
INCR16) are used where possible. 

When there is enough space and enough data to be transferred, the programmed fixed length bursts will be used.
If there is not enough data or space available, for example when at the beginning or the end of a buffer, SINGLE
type accesses are used. Also SINGLE type accesses are used at 1024 byte boundaries, so that the 1 Kbyte
boundaries are not burst over as per AHB requirements.

The DMA will not terminate a fixed length burst early, unless an error condition occurs on the AHB or if receive or
transmit are disabled in the Network Control Register.

The MAC transmitter can operate in either half duplex or full duplex mode and transmits frames in accordance with
the Ethernet IEEE 802.3 standard. In half duplex mode, the CSMA/CD protocol of the IEEE 802.3 specification is
followed.

A small input buffer receives data through FIFO which, depending on the DMA bus width control bits in the
Network Configuration Register, will extract data in 32-bit form. All subsequent processing prior to the final output
is performed in bytes.

Transmit data can be output using the MII interface.

Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from FIFO a word at a time. 

If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32-bit
polynomial. This is inverted and appended to the end of the frame taking the frame length to a minimum of 64
bytes. If the no CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor
CRC are appended. The no CRC bit can also be set through FIFO.

In full duplex mode (at all data rates), frames are transmitted immediately. Back to back frames are transmitted at
least 96 bit times apart to guarantee the interframe gap.

In half duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the signal to
become inactive, and then starts transmission after the interframe gap of 96 bit times. If the collision signal is
asserted during transmission, the transmitter will transmit a jam sequence of 32 bits taken from the data register
and then retry transmission after the back off time has elapsed. If the collision occurs during either the preamble or
Start Frame Delimiter (SFD), then these fields will be completed prior to generation of the jam sequence.

16

No CRC to be appended by MAC. When set, this implies that the data in the buffers 
already contains a valid CRC, hence no CRC or padding is to be appended to the current 
frame by the MAC. 

This control bit must be set for the first buffer in a frame and will be ignored for the 
subsequent buffers of a frame. 

Note that this bit must be clear when using the transmit IP/TCP/UDP checksum 
generation offload, otherwise checksum generation and substitution will not occur.

15

Last buffer, when set this bit will indicate the last buffer in the current frame has been 
reached.

14

Reserved

13:0

Length of buffer