Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート
製品コード
ATSAM4E-XPRO
1201
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Each discarded frame is counted in the 10 bit length field error statistics register. Frames where the length field is
greater than or equal to 0x0600 hex will not be checked.
greater than or equal to 0x0600 hex will not be checked.
43.5.6 Checksum Offload for IP, TCP and UDP
The GMAC can be programmed to perform IP, TCP and UDP checksum offloading in both receive and transmit
directions, which is enabled by setting bit 24 in the Network Configuration Register for receive.
directions, which is enabled by setting bit 24 in the Network Configuration Register for receive.
IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all
16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 1’s
complement of the 1’s complement sum of all 16-bit words in the header, the data and a conceptual IP pseudo
header.
16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 1’s
complement of the 1’s complement sum of all 16-bit words in the header, the data and a conceptual IP pseudo
header.
To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP
this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in
significant performance improvements.
this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in
significant performance improvements.
For IP, TCP or UDP checksum offload to be useful, the operating system containing the protocol stack must be
aware that this offload is available so that it can make use of the fact that the hardware can either generate or
verify the checksum.
aware that this offload is available so that it can make use of the fact that the hardware can either generate or
verify the checksum.
43.5.6.1 Receiver Checksum Offload
When receive checksum offloading is enabled in the GMAC, the IPv4 header checksum is checked as per RFC
791, where the packet meets the following criteria:
791, where the packet meets the following criteria:
If present, the VLAN header must be four octets long and the CFI bit must not be set.
Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP Encoding.
IPv4 packet
IP header is of a valid length
The GMAC also checks the TCP checksum as per RFC 793, or the UDP checksum as per RFC 768, if the
following criteria are met:
following criteria are met:
IPv4 or IPv6 packet
Good IP header checksum (if IPv4)
No IP fragmentation
TCP or UDP packet
When an IP, TCP or UDP frame is received, the receive buffer descriptor gives an indication if the GMAC was able
to verify the checksums. There is also an indication if the frame had SNAP encapsulation. These indication bits will
replace the type ID match indication bits when the receive checksum offload is enabled. For details of these
indication bits refer to
to verify the checksums. There is also an indication if the frame had SNAP encapsulation. These indication bits will
replace the type ID match indication bits when the receive checksum offload is enabled. For details of these
indication bits refer to
.
If any of the checksums are verified as incorrect by the GMAC, the packet is discarded and the appropriate
statistics counter incremented.
statistics counter incremented.
43.5.7 MAC Filtering Block
The filter block determines which frames should be written to FIFO and on to the optional DMA.
Whether a frame is passed depends on what is enabled in the Network Configuration Register, the state of the
external matching pins, the contents of the specific address, type and Hash Registers and the frame's destination
address and type field.
external matching pins, the contents of the specific address, type and Hash Registers and the frame's destination
address and type field.
If bit 25 of the Network Configuration Register is not set, a frame will not be copied to memory if the GMAC is
transmitting in half duplex mode at the time a destination address is received.
transmitting in half duplex mode at the time a destination address is received.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet
frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of
frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of