Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the
same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher
priority than FIQs to ensure that the transfer error does not escape detection.

Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an
interrupt from a peripheral.

When handling an ARM exception, the ARM9EJ-S core performs the following operations:

1.

Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new 
mode that has been entered. When the exception entry is from:

– ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current 

PC(r15) + 4 or PC + 8 depending on the exception).

– THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC 

+ 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place 
on return.

2.

Copies the CPSR into the appropriate SPSR.

3.

Forces the CPSR mode bits to a value that depends on the exception.

4.

Forces the PC to fetch the next instruction from the relevant exception vector.

The register r13 is also banked across exception modes to provide each exception handler with private stack
pointer.

The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.

When an exception has completed, the exception handler must move both the return value in the banked LR minus
an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This
action restores both PC and the CPSR.

The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the require-
ment for register saving which minimizes the overhead of context switching.

The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When
a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the excep-
tion until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example
because a branch occurs while it is in the pipeline, the abort does not take place.

The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the
Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction
reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs
while it is in the pipeline, the breakpoint does not take place.

The ARM instruction set is divided into:

• Branch instructions

• Data processing instructions

• Status register transfer instructions

• Load and Store instructions

• Coprocessor instructions

• Exception-generating instructions