Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート

 984

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Functional View of the Clock Generator Block Diagram 

 Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Man-

agement Controller (PMC). 

The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks avail-
able for all channels. Each channel can independently select one of the divided clocks.

The clock generator is divided in three blocks:

– a modulo n counter which provides 11 clocks: F

MCK

, F

MCK

/2, F

MCK

/4, F

MCK

/8, F

MCK

/16, F

MCK

/32, 

F

MCK

/64, F

MCK

/128, F

MCK

/256, F

MCK

/512, F

MCK

/1024 

– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB

Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock
to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting
clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR).

After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This
implies that after reset clkA (clkB) are turned off.

At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true
when the PWM master clock is turned off through the Power Management Controller.

modulo n counter

MCK

MCK/2
MCK/4

MCK/16
MCK/32
MCK/64

MCK/8

Divider A

clkA

DIVA

PWM_MR

MCK

MCK/128
MCK/256
MCK/512
MCK/1024

PREA

Divider B

clkB

DIVB

PWM_MR

PREB