Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD データシート
製品コード
ATSAM4S-WPIR-RD
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
88
12.6
Cortex-M4 Instruction Set
12.6.1 Instruction Set Summary
The processor implements a version of the Thumb instruction set.
lists the supported instructions.
Angle brackets, <>, enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 12-13.
Cortex-M4 Instructions
Mnemonic
Operands
Description
Flags
ADC, ADCS
{Rd,} Rn, Op2
Add with Carry
N,Z,C,V
ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V
ADD, ADDW
{Rd,} Rn, #imm12
Add
N,Z,C,V
ADR
Rd, label
Load PC-relative address
–
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
ASR, ASRS
Rd, Rm, <Rs|#n>
Arithmetic Shift Right
N,Z,C
B
label
Branch
–
BFC
Rd, #lsb, #width
Bit Field Clear
–
BFI
Rd, Rn, #lsb, #width
Bit Field Insert
–
BIC, BICS
{Rd,} Rn, Op2
Bit Clear
N,Z,C
BKPT
#imm
Breakpoint
–
BL
label
Branch with Link
–
BLX
Rm
Branch indirect with Link
–
BX
Rm
Branch indirect
–
CBNZ
Rn, label
Compare and Branch if Non Zero
–
CBZ
Rn, label
Compare and Branch if Zero
–
CLREX
–
Clear Exclusive
–
CLZ
Rd, Rm
Count leading zeros
–
CMN
Rn, Op2
Compare Negative
N,Z,C,V
CMP
Rn, Op2
Compare
N,Z,C,V
CPSID
i
Change Processor State, Disable Interrupts
–
CPSIE
i
Change Processor State, Enable Interrupts
–
DMB
–
Data Memory Barrier
–
DSB
–
Data Synchronization Barrier
–
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
–
Instruction Synchronization Barrier
–
IT
–
If-Then condition block
–