Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

The page buffer is not automatically reset after a page write. The programmer should do this
manually by issuing the Clear Page Buffer flash command. This can be done after a page write,
or before the page buffer is loaded with data to be stored to the flash page.

Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.
PAGEN will be updated with the value 1, and the word will be written into word 2 in the page
buffer.

This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an
entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be changed.
The procedure is as follows:

1.

Clear page buffer

2.

Write to the page buffer the result of the logical bitwise AND operation between the 
contents of the flash page and the new data to write. Only words that were in an erased 
state can be changed from the original page.

3.

Write Page. 

The None offers a command set to manage programming of the flash memory, locking and
unlocking of regions, and full flash erasing. See chapter 12.8.3 for a complete list of commands.

To run a command, the field CMD of the Flash Command Register (FCMD) has to be written
with the command number. As soon as the FCMD register is written, the FRDY flag is automati-
cally cleared. Once the current command is complete, the FRDY flag is automatically set. If an
interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash control-
ler is activated. All flash commands except for Quick Page Read (QPR) will generate an interrupt
request upon completion if FRDY is set.

After a command has been written to FCMD, the programming algorithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash will be busy. The waiting can be performed either by poll-
ing the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command
written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHC is
IDLE. The user must make sure that the access pattern to the FLASHC HSB interface contains
an IDLE cycle so that the command is allowed to start. Make sure that no bus masters such as
DMA controllers are performing endless burst transfers from the flash. Also, make sure that the
CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter
sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will
result in an access pattern with IDLE HSB cycles.

All the commands are protected by the same keyword, which has to be written in the eight high-
est bits of the FCMD register. Writing FCMD with data that does not contain the correct key
and/or with an invalid command has no effect on the flash memory; however, the PROGE flag is
set in the Flash Status Register (FSR). This flag is automatically cleared by a read access to the
FSR register.

Writing a command to FCMD while another command is being executed has no effect on the
flash memory; however, the PROGE flag is set in the Flash Status Register (FSR). This flag is
automatically cleared by a read access to the FSR register.