Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

3.

The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is 
empty. 

When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit
is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single
word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel
FIFO but not enough to form a single transfer of CTLx.DST_TR_WIDTH width. In this configura-
tion, once the channel is disabled, the remaining data in the channel FIFO are not transferred to
the destination peripheral. It is permitted to remove the channel from the suspension state by
writing a ‘0’ to the CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.

Note:

If a channel is disabled by software, an active single or burst transaction is not guaranteed to 
receive an acknowledgement.

A DMACA DMA transfer may be terminated abruptly by software by clearing the channel enable
bit, ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the
ChEnReg.CH_EN bit is cleared over the HSB slave interface. Consider this as a request to dis-
able the channel. The ChEnReg.CH_EN must be polled and then it must be confirmed that the
channel is disabled by reading back 0. A case where the channel is not be disabled after a chan-
nel disable request is where either the source or destination has received a split or retry
response. The DMACA must keep re-attempting the transfer to the system HADDR that origi-
nally received the split or retry response until an OKAY response is returned. To do otherwise is
an System Bus protocol violation.

Software may terminate all channels abruptly by clearing the global enable bit in the DMACA
Configuration Register (DmaCfgReg[0]). Again, this does not mean that all channels are dis-
abled immediately after the DmaCfgReg[0] is cleared over the HSB slave interface. Consider
this as a request to disable all channels. The ChEnReg must be polled and then it must be con-
firmed that all channels are disabled by reading back ‘0’.

Note:

If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to 
the destination peripheral and is not present when the channel is re-enabled. For read sensitive 
source peripherals such as a source FIFO this data is therefore lost. When the source is not a 
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to 
empty may be acceptable as the data is available from the source peripheral upon request and is 
not lost.

Note:

If a channel is disabled by software, an active single or burst transaction is not guaranteed to 
receive an acknowledgement.