Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
360
32072H–AVR32–10/2012
AT32UC3A3
19.12.7
Configuration Register for Channel x High
Name: CFGxH
Access Type: Read/Write
Offset:
0x044 + [x * 0x58]
Reset Value:
0x00000004
• DEST_PER: Destination Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the
CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the destination
peripheral connected to that interface via the assigned hardware handshaking interface.
CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the destination
peripheral connected to that interface via the assigned hardware handshaking interface.
For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
interface.
• SRC_PER: Source Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the
CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source periph-
eral connected to that interface via the assigned hardware handshaking interface.
CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source periph-
eral connected to that interface via the assigned hardware handshaking interface.
For correct DMACA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
interface.
• PROTCTL: Protection Control
Bits used to drive the System Bus HPROT[3:1] bus. The System Bus Specification recommends that the default value of
HPROT indicates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access.
HPROT indicates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access.
HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches. There is a one-to-one mapping of
these register bits to the HPROT[3:1] master interface signals.
these register bits to the HPROT[3:1] master interface signals.
• FIFO_MODE: R/W 0x0 FIFO Mode Select
Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced.
0 = Space/data available for single System Bus transfer of the specified transfer width.
1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO
depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
-
DEST_PER
SRC_PER[3:1]
7
6
5
4
3
2
1
0
SRC_PER[0]
-
-
PROTCTL
FIFO_MODE
FCMODE