Intel 1020E AV8063801276200 ユーザーズマニュアル

Datasheet, Volume 1

27

Interfaces

The following sections describe the Just-in-Time Scheduling, Command Overlap, and 
Out-of-Order Scheduling Intel FMA technology enhancements.

The memory controller has an advanced command scheduler where all pending 
requests are examined simultaneously to determine the most efficient request to be 
issued next. The most efficient request is picked from all pending requests and issued 
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus, 
instead of having all memory access requests go individually through an arbitration 
mechanism forcing requests to be executed one at a time, they can be started without 
interfering with the current request allowing for concurrent issuing of requests. This 
allows for optimized bandwidth and reduced latency while maintaining appropriate 
command spacing to meet system memory protocol.

Command Overlap allows the insertion of the DRAM commands between the Activate, 
Precharge, and Read/Write commands normally used, as long as the inserted 
commands do not affect the currently executing command. Multiple commands can be 
issued in an overlapping manner, increasing the efficiency of system memory protocol.

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, 
the IMC continuously monitors pending requests to system memory for the best use of 
bandwidth and reduction of latency. If there are multiple requests to the same open 
page, these requests would be launched in a back to back manner to make optimum 
use of the open memory page. This ability to reorder requests on the fly allows the IMC 
to further reduce latency and increase bandwidth efficiency.

The memory controller incorporates a DDR3 Data Scrambling feature to minimize the 
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the 
data bus. Past experience has demonstrated that traffic on the data bus is not random. 
Rather, it can have energy concentrated at specific spectral harmonics creating high 
di/dt that is generally limited by data patterns that excite resonance between the 
package inductance and on die capacitances. As a result the memory controller uses a 
data scrambling feature to create pseudo-random patterns on the DDR3 data bus to 
reduce the impact of any excessive di/dt.

The processor memory controller has the capability of generating the DDR3 Reference 
Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The 
generated VREF can be changed in small steps, and an optimum VREF value is 
determined for both during a cold boot through advanced DDR3 training procedures in 
order to provide the best voltage and signal margins.