Intel i5-4200H CL8064701470601 データシート
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製品コード
CL8064701470601
programmers through the RDRAND instruction. The resultant random number
generation capability is designed to comply with existing industry standards in this
regard (ANSI X9.82 and NIST SP 800-90).
Some possible usages of the RDRAND instruction include cryptographic key generation
as used in a variety of applications, including communication, digital signatures,
secure storage, and so on.
Intel
®
Transactional Synchronization Extensions - New
Instructions (Intel
®
TSX-NI)
Intel Transactional Synchronization Extensions - New Instructions (Intel TSX-NI). Intel
TSX-NI provides a set of instruction extensions that allow programmers to specify
regions of code for transactional synchronization. Programmers can use these
extensions to achieve the performance of fine-grain locking while actually
programming using coarse-grain locks. Details on Intel TSX-NI are in the Intel
®
Architecture Instruction Set Extensions Programming Reference.
Intel
®
64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides key
mechanisms for interrupt delivery. This extension is primarily intended to increase
processor addressability.
Specifically, x2APIC:
•
•
Retains all key elements of compatibility to the xAPIC architecture:
— Delivery modes
— Interrupt and processor priorities
— Interrupt sources
— Interrupt destination types
— Delivery modes
— Interrupt and processor priorities
— Interrupt sources
— Interrupt destination types
•
Provides extensions to scale processor addressability for both the logical and
physical destination modes
•
Adds new features to enhance performance of interrupt delivery
•
Reduces complexity of logical destination mode interrupt delivery on link based
architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
•
•
Support for two modes of operation to provide backward compatibility and
extensibility for future platform innovations:
— In xAPIC compatibility mode, APIC registers are accessed through memory
— In xAPIC compatibility mode, APIC registers are accessed through memory
mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
— In x2APIC mode, APIC registers are accessed through Model Specific Register
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly
increased processor addressability and some enhancements on interrupt
delivery.
•
Increased range of processor addressability in x2APIC mode:
3.7
3.8
Processor—Technologies
Mobile 4th Generation Intel
®
Core
™
Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2
July 2014
48
Order No.: 328901-007