Oracle Vacuum Cleaner CPU-56T ユーザーズマニュアル

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Devices’ Features and Data Paths
PCI Bus A
78
SPARC/CPU−56T
S Integral FIFOs for write posting to maximize bandwidth utilization
S Programmable DMA controller with linked−list mode
S CPU or peripheral boards functioning as both master and slave in the
S Sustained transfer rates up to 60−70 Mbytes/s
Note:
a
When operating the board in system slot 1, the system clock is disabled while
the board is in reset. This is a limitation of the Universe II device.
a