Nxp Semiconductors LPC2917 ユーザーズマニュアル

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

 

The timer modules are clocked by two different clocks; CLK_SYS_PESS and CLK_TMRx 
(x = 0-3), see 

. Note that each timer has its own CLK_TMRx branch clock for 

power management. The frequency of all these clocks is identical as they are derived 
from the same base clock BASE_CLK_TMR. The register interface towards the system 
bus is clocked by CLK_SYS_PESS. The timer and prescale counters are clocked by 
CLK_TMRx.

The LPC2917/19 contains two identical UARTs located at different peripheral base 
addresses. The key features are:

16-byte receive and transmit FIFOs

Registers conform to industry standard 550 

Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes

Built-in baud-rate generator

The UART is commonly used to implement a serial interface such as RS232. The 
LPC2917/19 contains two industry-standard 550 UARTs with 16-byte transmit and receive 
FIFOs, but they can also be put into 450 mode without FIFOs.

The two UARTs in the LPC2917/19 have the following pins. The UART pins are combined 
with other functions on the port pins of the LPC2917/19. 

 shows the UART pins (x 

runs from 0 to 1).

 

TIMERx CAP[0]

IN

TIMER x capture input 0

TIMERx CAP[1]

IN

TIMER x capture input 1

TIMERx CAP[2]

IN

TIMER x capture input 2

TIMERx CAP[3]

IN

TIMER x capture input 3

TIMERx MAT[0]

OUT

TIMER x match output 0

TIMERx MAT[1]

OUT

TIMER x match output 1

TIMERx MAT[2]

OUT

TIMER x match output 2

TIMERx MAT[3]

OUT

TIMER x match output 3

UARTx TXD

out

UART channel x transmit data output

UARTx RXD

in

UART channel x receive data input