Nxp Semiconductors LPC2917 ユーザーズマニュアル

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

See section 

 for a description of the timers.

MSCSS timer 0 has no external pins.

MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined 
with other functions on the port pins of the LPC2917/19. 

 shows the MSCSS 

timer 1 external pin.

 

The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx (x = 0-1), see 

. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for 

power management. The frequency of all these clocks is identical to CLK_MSCSS_VPB 
since they are derived from the same base clock BASE_MSCSS_CLK.

Note that, unlike the timer modules in the Peripheral SubSystem, the actual timer counter 
registers run at the same clock as the VPB system interface CLK_MSCSS_VPB. This 
clock is independent of the AHB system clock. 

If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off.

The Power, Clock and Reset Control Subsystem (PCRSS) in the LPC2917/19 includes a 
Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management 
Unit (PMU).

 provides an overview of the PCRSS. An AHB-to-DTL bridge takes care of 

communication with the AHB system bus.

MSCSS PAUSE

in

pause pin for MSCSS timer 1