Nxp Semiconductors LPC2917 ユーザーズマニュアル

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Interrupt-request masking is performed individually per interrupt target by comparing the 
priority level assigned to a specific interrupt request with a target-specific priority 
threshold. The priority levels are defined as follows:

Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never 
lead to an interrupt)

Priority 1 corresponds to the lowest priority

Priority 15 corresponds to the highest priority

Software interrupt support is provided and can be supplied for:

Testing RTOS interrupt handling without using device-specific interrupt service 
routines

Software emulation of an interrupt-requesting device, including interrupts

The VIC module in the LPC2917/19 has no external pins.

The VIC is clocked by CLK_SYS_VIC, see 

 

P

tot

Total power dissipation.

-

1

W

V

DD(CORE)

Core supply voltage.

−0.5

+2.0

V

V

DD(OSC_PLL)

Oscillator and PLL supply 
voltage.

−0.5

+2.0

V

V

DD(ADC3V3)

3.3 V ADC supply voltage.

−0.5

+4.6

V

V

DD(IO)

I/O digital supply voltage.

−0.5

+4.6

V

I

DD

Supply current.

Average value per supply 
pin.

-

98

mA

I

SS

Ground current.

Average value per ground 
pin.

-

98

mA

V

XIN_OSC

Voltage on pin XIN_OSC.

−0.5

+2.0

V

V

XIN_RTC

Voltage on pin XIN_RTC.

−0.5

+2.0

V

V

I(IO)

I/O input voltage.

−0.5

V

DD(IO)

+ 3.0

V

V

I(ADC)

ADC input voltage.

I/O port 0. 

−0.5

V

DD(ADC3V3)

+ 0.5

V

V

VREFP

Voltage on pin VREFP.

−0.5

+3.6

V

V

VREFN

Voltage on pin VREFN.

−0.5

+3.6

V

I

I(ADC)

ADC input current.

Average value per input pin.

-

35

mA