AMD Am186TMER ユーザーズマニュアル
Interrupt Control Unit
8-15
Bits 2–0: Priority Level (PR2–PR0)—This field determines the priority of INT0 or INT1
relative to the other interrupt signals, as shown in Table 8-3, “Priority Level,” on page 8-15.
relative to the other interrupt signals, as shown in Table 8-3, “Priority Level,” on page 8-15.
Table 8-3
Priority Level
Priority
PR2–PR0
(High) 0
0 0 0b
1
0 0 1b
2
0 1 0b
3
0 1 1b
4
1 0 0b
5
1 0 1b
6
1 1 0b
(Low) 7
1 1 1b