ユーザーズマニュアル目次Help Questions3Customer Service3Hotline/World Wide Web Support3Documentation and Literature3Table of Contents5List of Figures9List of Tables11Introduction and Overview13Design Philosophy13Purpose of this Manual13Intended Audience13User’s Manual Overview13AMD Documentation14Chap 1:Features and Performance151.1 Key Features and Benefits151.2 Distinctive Characteristics16Figure 1-1 Am186ER Microcontroller Block Diagram18Figure 1-2 Am188ER Microcontroller Block Diagram191.3 Application Considerations20Figure 1-3 Basic Functional System Design201.3.1 Clock Generation201.3.2 Memory Interface211.3.3 Serial Communications Port211.4 Third-Party Development Support Products22Chap 2:Programming232.1 Register Set23Figure 2-1 Register Set242.1.1 Processor Status Flags Register24Figure 2-2 Processor Status Flags Register (FLAGS)242.2 Memory Organization and Address Generation25Figure 2-3 Physical Address Generation262.3 I/O Space26Figure 2-4 Memory and I/O Space262.4 Instruction Set26Table 2-1 Instruction Set272.5 Segments30Table 2-2 Segment Register Selection Rules302.6 Data Types30Figure 2-5 Supported Data Types312.7 Addressing Modes32Register and Immediate Operands32Memory Operands32Table 2-3 Memory Addressing Mode Examples32Chap 3:System Overview333.1 Pin Descriptions33A19–A033AD7–AD033AD15–AD834AO15–AO834CLKOUTB36DEN36DRQ1–DRQ036ALE34ARDY35BHE/ADEN35CLKOUTA36DT/R36GND36HLDA36HOLD37INT037INT1/SELECT37INT2/INTA038INT3/INTA1/IRQ38INT438LCS/ONCE039MCS3/RFSH39MCS2–MCS039NMI39PCS3–PCS040PCS5/A140PCS6/A240PIO31–PIO041Table 3-1 PIO Pin Assignments—Numeric Listing42Table 3-2 PIO Pin Assignments—Alphabetic Listing43RD44RES44RFSH2/ADEN44RXD44S245S1/IMDIS45S0/SREN45Table 3-3 Bus Cycle Encoding45S6/CLKSEL145SCLK46SDATA46SDEN1–SDEN046SRDY46TMRIN046TMRIN147TMROUT047TMROUT147TXD47UCS/ONCE147UZI/CLKSEL247Table 3-4 Clocking Modes48VCC48WHB48WLB/WB48WR49X149X2493.1.1 Pins That Are Used by Emulators493.2 Bus Operation50Figure 3-1 Am186ER Microcontroller Address Bus—Nor...51Figure 3-2 Am186ER Microcontroller—Read and Write ...51Figure 3-3 Am188ER Microcontroller Address Bus—Nor...52Figure 3-4 Am188ER Microcontroller—Read and Write ...523.3 Bus Interface Unit533.3.1 Nonmultiplexed Address Bus533.3.2 Byte Write Enables533.3.3 Pseudo Static RAM (PSRAM) Support533.4 Clock and Power Management Unit553.4.1 Phase-Locked Loop (PLL)55Table 3-5 Maximum and Minimum Clock Frequencies553.4.2 Crystal-Driven Clock Source56Figure 3-5 Oscillator Configurations563.4.3 External Source Clock563.4.4 System Clocks57Figure 3-6 Clock Organization573.4.5 Power-Save Operation57Chap 4:Peripheral Control Block594.1 Overview59Figure 4-1 Peripheral Control Block Register Map604.1.1 Peripheral Control Block Relocation Register62Figure 4-2 PCB Relocation Register624.1.2 Reset Configuration Register63Figure 4-3 Reset Configuration Register634.1.3 Processor Release Level Register64Figure 4-4 Processor Release Level Register64Table 4-1 PRL Values644.1.4 Power-Save Control Register65Figure 4-5 Power-Save Control Register654.2 Initialization and Processor Reset66Table 4-2 Initial Register State After Reset67Chap 5:Chip Select Unit695.1 Overview69Table 5-1 Chip Select Register Summary695.2 Chip Select Timing705.3 Ready and Wait-State Programming705.4 Chip Select Overlap705.5 Chip Select Registers715.5.1 Upper Memory Chip Select Register (UMCS)72Figure 5-1 Upper Memory Chip Select Register72Table 5-2 UMCS Block Size Programming Values725.5.2 Low Memory Chip Select Register (LMCS)74Figure 5-2 Low Memory Chip Select Register74Table 5-3 LMCS Block Size Programming Values745.5.3 Midrange Memory Chip Select Register (MMCS)76Figure 5-3 Midrange Memory Chip Select Register765.5.4 PCS and MCS Auxiliary Register (MPCS)78Figure 5-4 PCS and MCS Auxiliary Register78Table 5-4 MCS Block Size Programming785.5.5 Peripheral Chip Select Register (PACS)80Figure 5-5 Peripheral Chip Select Register80Table 5-5 PCS Address Ranges81Table 5-6 PCS3–PCS0 Wait-State Encoding81Chap 6:Internal Memory836.1 Overview836.2 Interaction with External RAM836.3 Emulator and Debug Modes846.3.1 Internal Memory Disable846.3.2 Show Read Enable846.4 Internal Memory Chip Select Register (IMCS)85Figure 6-1 Internal Memory Chip Select Register85Chap 7:Refresh Control Unit877.1 Overview877.1.1 Memory Partition Register (MDRAM)87Figure 7-1 Memory Partition Register877.1.2 Clock Prescaler Register (CDRAM)88Figure 7-2 Clock Prescaler Register887.1.3 Enable RCU Register (EDRAM)88Figure 7-3 Enable RCU Register88Chap 8:Interrupt Control Unit898.1 Overview898.1.1 Definitions of Interrupt Terms89Table 8-1 Interrupt Types918.1.2 Interrupt Conditions and Sequence928.1.3 Interrupt Priority938.1.4 Software Exceptions, Traps, and NMI948.1.5 Interrupt Acknowledge96Figure 8-1 Interrupt Acknowledge Bus Cycle968.1.6 Interrupt Controller Reset Conditions978.2 Master Mode Operation988.2.1 Fully Nested Mode98Figure 8-2 Fully Nested Mode Interrupt Connections988.2.2 Cascade Mode99Figure 8-3 Cascade Mode Interrupt Connections998.2.3 Special Fully Nested Mode1008.2.4 Operation in a Polled Environment1008.2.5 End-of-Interrupt Write to the EOI Register1008.3 Master Mode Interrupt Controller Registers101Table 8-2 Interrupt Control Registers, Master Mode1018.3.1 INT0 and INT1 Control Registers (I0CON)102Figure 8-4 INT0 and INT1 Control Registers102Table 8-3 Priority Level1038.3.2 INT2 and INT3 Control Registers (I2CON)104Figure 8-5 INT2 and INT3 Control Registers1048.3.3 INT4 Control Register (I4CON)105Figure 8-6 INT4 Control Register1058.3.4 Timer and DMA Interrupt Control Registers106Figure 8-7 Timer/DMA Interrupt Control Registers1068.3.5 Watchdog Timer Interrupt Control Register107Figure 8-8 Watchdog Timer Interrupt Control1078.3.6 Serial Port Interrupt Control Register108Figure 8-9 Serial Port Interrupt Control Register1088.3.7 Interrupt Status Register (INTSTS)109Figure 8-10 Interrupt Status Register1098.3.8 Interrupt Request Register (REQST)110Figure 8-11 Interrupt Request Register1108.3.9 In-Service Register (INSERV)111Figure 8-12 In-Service Register1118.3.10 Priority Mask Register (PRIMSK)112Figure 8-13 Priority Mask Register112Table 8-4 Priority Field Mask (Master Mode)1128.3.11 Interrupt Mask Register (IMASK)113Figure 8-14 Interrupt Mask Register1138.3.12 Poll Status Register (POLLST)114Figure 8-15 Poll Status Register1148.3.13 Poll Register (POLL)115Figure 8-16 Poll Register (POLL)1158.3.14 End-of-Interrupt Register (EOI)116Figure 8-17 Example EOI Assembly Code116Figure 8-18 End-of-Interrupt Register1168.4 Slave Mode Operation1178.4.1 Slave Mode Interrupt Nesting1178.4.2 Slave Mode Interrupt Controller Registers117Table 8-5 Interrupt Controller Registers, Slave Mode1178.4.3 Timer and DMA Interrupt Control Registers118Figure 8-19 Timer and DMA Interrupt Control Registers1188.4.4 Interrupt Status Register (INTSTS)119Figure 8-20 Interrupt Status Register1198.4.5 Interrupt Request Register (REQST)120Figure 8-21 Interrupt Request Register1208.4.6 In-Service Register (INSERV)121Figure 8-22 In-Service Register1218.4.7 Priority Mask Register (PRIMSK)122Figure 8-23 Priority Mask Register122Table 8-6 Priority Field Mask (Slave Mode)1228.4.8 Interrupt Mask Register (IMASK)123Figure 8-24 Interrupt Mask Register1238.4.9 Specific End-of-Interrupt Register (EOI)124Figure 8-25 Specific End-of-Interrupt Register1248.4.10 Interrupt Vector Register (INTVEC)125Figure 8-26 Interrupt Vector Register125Chap 9:Timer Control Unit1279.1 Overview1279.2 Programmable Registers127Table 9-1 Timer Control Unit Register Summary1279.2.1 Timer Operating Frequency1289.2.2 Timer 0 and Timer 1 Mode and Control Registers129Figure 9-1 Timer 0 and Timer 1 Mode and Control1299.2.3 Timer 2 Mode and Control Register131Figure 9-2 Timer 2 Mode and Control Register1319.2.4 Timer Count Registers132Figure 9-3 Timer Count Registers1329.2.5 Timer Maxcount Compare Registers133Figure 9-4 Timer Maxcount Compare Registers133Chap 10:DMA Controller13510.1 Overview13510.2 DMA Operation135Table 10-1 DMA Controller Register Summary135Figure 10-1 DMA Unit Block Diagram13610.3 Programmable DMA Registers13610.3.1 DMA Control Registers (D0CON)137Figure 10-2 DMA Control Registers137Table 10-2 Synchronization Type13810.3.2 DMA Transfer Count Registers (D0TC)139Figure 10-3 DMA Transfer Count Registers13910.3.3 DMA Destination Address High Register140Figure 10-4 DMA Destination Address High Register ...14010.3.4 DMA Destination Address Low Register141Figure 10-5 DMA Destination Address Low Register14110.3.5 DMA Source Address High Register142Figure 10-6 DMA Source Address High Register14210.3.6 DMA Source Address Low Register143Figure 10-7 DMA Source Address Low Register14310.4 DMA Requests144Table 10-3 Maximum DMA Transfer Rates14410.4.1 Synchronization Timing145Figure 10-8 Source-Synchronized DMA Transfers145Figure 10-9 Destination Synchronized DMA Transfers14610.4.2 DMA Acknowledge14610.4.3 DMA Priority14610.4.4 DMA Programming14610.4.5 DMA Channels on Reset147Chap 11:Asynchronous Serial Port14911.1 Overview14911.2 Programmable Registers149Table 11-1 Asynchronous Serial Port Register Summary14911.2.1 Serial Port Control Register (SPCT)150Figure 11-1 Serial Port Control Register150Table 11-2 Parity Mode Bit Settings15111.2.2 Serial Port Status Register (SPSTS)152Figure 11-2 Serial Port Status Register15211.2.3 Serial Port Transmit Data Register (SPTD)153Figure 11-3 Serial Port Transmit Data Register15311.2.4 Serial Port Receive Data Register (SPRD)154Figure 11-4 Serial Port Receive Data Register15411.2.5 Serial Port Baud Rate Divisor Register (SPBAUD)155Figure 11-5 Serial Port Baud Rate Divisor Register155Table 11-3 Serial Port Baud Rate Table155Chap 12:Synchronous Serial Interface15712.1 Overview157Table 12-1 Synchronous Serial Interface Summary15712.1.1 Four-Pin Interface15812.2 Programmable Registers15812.2.1 Synchronous Serial Status Register159Figure 12-1 Synchronous Serial Status Register15912.2.2 Synchronous Serial Control Register160Figure 12-2 Synchronous Serial Control Register160Table 12-2 SCLK Divider Values16012.2.3 Synchronous Serial Transmit 1 Register161Figure 12-3 Synchronous Serial Transmit Register16112.2.4 Synchronous Serial Receive Register162Figure 12-4 Synchronous Serial Receive Register16212.3 SSI Programming163Figure 12-5 SSI Multiple Write164Figure 12-6 SSI Multiple Read164Chap 13:Programmable I/O Pins16513.1 Overview165Figure 13-1 Programmable I/O Pin Operation165Table 13-1 PIO Pin Assignments and Register Bits16613.2 PIO Mode Registers167Table 13-2 PIO Mode and PIO Direction Settings167Figure 13-2 PIO Mode 1 Register (PIOMODE1)167Figure 13-3 PIO Mode 0 Register (PIOMODE0)16713.2.1 PIO Mode 1 Register16713.2.2 PIO Mode 0 Register16713.3 PIO Direction Registers168Figure 13-4 PIO Direction 1 Register (PDIR1)168Figure 13-5 PIO Direction 0 Register (PDIR0)16813.3.1 PIO Direction 1 Register16813.3.2 PIO Direction 0 Register16813.4 PIO Data Registers169Figure 13-6 PIO Data 1 Register (PDATA1)169Figure 13-7 PIO Data 0 Register (PDATA0)16913.4.1 PIO Data Register 116913.4.2 PIO Data Register 016913.5 Open-Drain Outputs169Appendix A:Register Summary171Table A-1 Internal Register Summary172Figure A-1 Internal Register Summary174Index187サイズ: 2.77MBページ数: 196Language: Englishマニュアルを開く