AMD Am186TMER ユーザーズマニュアル
Interrupt Control Unit
8-21
8.3.7
Interrupt Status Register (INTSTS, Offset 30h)
(Master Mode)
(Master Mode)
The Interrupt Status (INTSTS) Register indicates the interrupt request status of the three
timers.
timers.
Figure 8-10
Interrupt Status Register (INTSTS, offset 30h)
Bit 15: DMA Halt (DHLT)—When set to 1, halts any DMA activity. This bit is automatically
set to 1 when nonmaskable interrupts occur and is reset when an IRET instruction is
executed. Time-critical software, such as interrupt handlers, can modify this bit directly to
inhibit DMA transfers. Because of the function of this register as an interrupt request register
for the timers, the DHLT bit should not be modified by software when timer interrupts are
enabled.
set to 1 when nonmaskable interrupts occur and is reset when an IRET instruction is
executed. Time-critical software, such as interrupt handlers, can modify this bit directly to
inhibit DMA transfers. Because of the function of this register as an interrupt request register
for the timers, the DHLT bit should not be modified by software when timer interrupts are
enabled.
Bits 14–3: Reserved
Bits 2–0: Timer Interrupt Request (TMR2–TMR0)—When set to 1, these bits indicate
that the corresponding timer has an interrupt request pending. (Note that the timer TMR
bit in the REQST Register is the logical OR of these timer interrupt requests.)
that the corresponding timer has an interrupt request pending. (Note that the timer TMR
bit in the REQST Register is the logical OR of these timer interrupt requests.)
15
7
0
Reserved
TMR2
TMR1
TMR0
DHLT